Searched refs:FP64 (Results 1 - 6 of 6) sorted by relevance
| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.h | 111 MachineBasicBlock::iterator I, bool FP64) const;
113 MachineBasicBlock::iterator I, bool FP64) const;
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| H A D | MipsSEFrameLowering.cpp | 69 MachineBasicBlock::iterator I, bool FP64) const;
71 MachineBasicBlock::iterator I, bool FP64) const;
270 bool FP64) const {
284 (FP64 && !Subtarget.useOddSPReg())) {
297 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
322 bool FP64) const {
346 (FP64 && !Subtarget.useOddSPReg())) {
359 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
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| H A D | MipsSEInstrInfo.cpp | 588 bool FP64) const {
602 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
619 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
627 bool FP64) const {
653 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
672 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
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| /freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 49 WebAssembly::FP64})
99 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUSubtarget.h | 68 bool FP64; member in class:llvm::AMDGPUSubtarget
143 return FP64;
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| H A D | AMDGPUSubtarget.cpp | 39 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
71 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
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