Searched refs:Def1 (Results 1 - 4 of 4) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp71 MachineInstr *Def1, *Def2; member in struct:__anon2864::HexagonGenMux::MuxInfo
75 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(D1),
261 MachineInstr *Def1 = It1, *Def2 = It2; local
262 MachineOperand *Src1 = &Def1->getOperand(2), *Src2 = &Def2->getOperand(2);
284 MachineBasicBlock::iterator At = CanDown ? Def2 : Def1;
285 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2));
299 B.erase(MX.Def1);
H A DHexagonEarlyIfConv.cpp446 MachineInstr *Def1 = MRI->getVRegDef(RO1.getReg()); local
448 if (!TII->isPredicable(Def1) || !TII->isPredicable(Def3))
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp1517 MachineInstr *Def1 = MRI->getVRegDef(Addr1); local
1520 if (!produceSameValue(Def0, Def1, MRI))
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4045 bool Def1 = (Elems[I1].getOpcode() != ISD::UNDEF);
4047 if (Def1 || Def2) {
4048 SDValue Elem1 = Elems[Def1 ? I1 : I2];

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