Searched refs:CSR_READ_1 (Results 1 - 25 of 47) sorted by relevance

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/freebsd-11.0-release/sys/dev/ex/
H A Dif_ex.c327 temp_reg = CSR_READ_1(sc, EEPROM_REG);
339 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr);
340 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem);
341 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ );
350 (CSR_READ_1(sc, INT_NO_REG) & 0xf8) |
372 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT);
600 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT);
631 (int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) {
767 *(mtod(m, caddr_t) + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG);
885 CSR_WRITE_1(sc, REG2, CSR_READ_1(s
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H A Dif_ex_isa.c330 if (((count1 = CSR_READ_1(sc, ID_REG)) & Id_Mask) != Id_Sig)
332 count2 = CSR_READ_1(sc, ID_REG);
333 count2 = CSR_READ_1(sc, ID_REG);
334 count2 = CSR_READ_1(sc, ID_REG);
H A Dif_exvar.h95 #define CSR_READ_1(sc, off) (bus_read_1((sc)->ioport, off)) macro
/freebsd-11.0-release/sys/dev/vx/
H A Dif_vxvar.h71 #define CSR_READ_1(sc, reg) \ macro
/freebsd-11.0-release/sys/dev/ste/
H A Dif_ste.c197 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
213 val = CSR_READ_1(sc, STE_PHYCTL);
418 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
453 CSR_READ_1(sc, STE_RX_MODE);
814 CSR_READ_1(sc, STE_STAT_RX_BCAST);
815 CSR_READ_1(sc, STE_STAT_RX_MCAST);
816 CSR_READ_1(sc, STE_STAT_RX_LOST);
821 CSR_READ_1(sc, STE_STAT_TX_BCAST);
822 CSR_READ_1(s
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/freebsd-11.0-release/sys/dev/sn/
H A Dif_snvar.h58 #define CSR_READ_1(sc, off) (bus_read_1((sc)->port_res, off)) macro
H A Dif_sn.c453 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
467 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
479 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
549 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
662 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
747 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
810 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
817 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
992 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
1086 *data = CSR_READ_1(s
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/freebsd-11.0-release/sys/dev/vge/
H A Dif_vgevar.h228 #define CSR_READ_1(sc, reg) \ macro
232 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
239 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
H A Dif_vge.c260 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
301 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
314 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
334 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
351 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
379 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
415 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
484 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
522 cfg = CSR_READ_1(sc, VGE_RXCFG);
550 rxcfg = CSR_READ_1(s
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/freebsd-11.0-release/sys/dev/bm/
H A Dif_bmreg.h166 #define CSR_READ_1(sc, reg) \ macro
/freebsd-11.0-release/sys/dev/tx/
H A Dif_txvar.h140 #define CSR_READ_1(sc, reg) \ macro
/freebsd-11.0-release/sys/dev/re/
H A Dif_re.c350 CSR_READ_1(sc, RL_EECMD) | x)
354 CSR_READ_1(sc, RL_EECMD) & ~x)
404 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
449 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
547 rval = CSR_READ_1(sc, RL_MEDIASTAT);
730 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
1313 cfg = CSR_READ_1(sc, RL_CFG2);
1350 cfg = CSR_READ_1(sc, RL_CFG2);
1545 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1548 cfg = CSR_READ_1(s
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/freebsd-11.0-release/sys/dev/vr/
H A Dif_vr.c255 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
279 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
324 cr0 = CSR_READ_1(sc, VR_CR0);
325 cr1 = CSR_READ_1(sc, VR_CR1);
349 fc = CSR_READ_1(sc, VR_FLOWCR1);
362 fc = CSR_READ_1(sc, VR_MISC_CR0);
421 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)
450 rxfilt = CSR_READ_1(sc, VR_RXCFG);
533 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET))
718 if ((CSR_READ_1(s
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H A Dif_vrreg.h756 #define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) macro
758 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
759 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-11.0-release/sys/dev/rl/
H A Dif_rl.c267 CSR_READ_1(sc, RL_EECMD) | x)
271 CSR_READ_1(sc, RL_EECMD) & ~x)
325 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
367 val = CSR_READ_1(sc, RL_MII);
424 return (CSR_READ_1(sc, RL_MEDIASTAT));
572 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
777 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1143 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1929 if ((CSR_READ_1(sc, RL_COMMAND) &
2066 v = CSR_READ_1(s
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H A Dif_rlreg.h959 #define CSR_READ_1(sc, reg) \ macro
966 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
/freebsd-11.0-release/sys/dev/fxp/
H A Dif_fxpvar.h244 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) macro
H A Dif_fxp.c335 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
338 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
339 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
341 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
342 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
343 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
919 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
1117 CSR_READ_1(sc, FXP_CSR_PMDR));
1694 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1733 while ((statack = CSR_READ_1(s
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/freebsd-11.0-release/sys/dev/ep/
H A Dif_epvar.h86 #define CSR_READ_1(sc, off) (bus_space_read_1((sc)->bst, (sc)->bsh, off)) macro
H A Dif_ep.c427 CSR_READ_1(sc, EP_W1_TX_STATUS);
670 while ((status = CSR_READ_1(sc, EP_W1_TX_STATUS)) &
808 CSR_READ_1(sc, EP_W1_RX_PIO_RD_1);
/freebsd-11.0-release/sys/dev/ipw/
H A Dif_ipwreg.h325 #define CSR_READ_1(sc, reg) \ macro
352 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
/freebsd-11.0-release/sys/dev/xl/
H A Dif_xl.c454 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
617 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
665 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
818 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
2091 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2314 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2330 CSR_READ_1(sc, XL_W4_BADSSD);
2829 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2955 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2964 if (CSR_READ_1(s
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/freebsd-11.0-release/sys/dev/wb/
H A Dif_wbreg.h379 #define CSR_READ_1(sc, reg) bus_read_1(sc->wb_res, reg) macro
/freebsd-11.0-release/sys/dev/msk/
H A Dif_msk.c1207 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
1669 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1783 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1784 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1821 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1824 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1826 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3422 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3850 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
4105 CSR_READ_1(s
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/freebsd-11.0-release/sys/dev/stge/
H A Dif_stge.c257 val = CSR_READ_1(sc, STGE_PhyCtrl);
296 error = CSR_READ_1(sc, STGE_PhyCtrl);
593 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
989 v = CSR_READ_1(sc, STGE_WakeEvent);
1035 v = CSR_READ_1(sc, STGE_WakeEvent);
1958 v = CSR_READ_1(sc, STGE_PhySet);

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