Searched refs:CC2 (Results 1 - 4 of 4) sorted by relevance
| /freebsd-11.0-release/contrib/gcc/config/s390/ |
| H A D | s390.c | 474 CC1 and CC2 for mixed selected bits (TMxx), it is false
496 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
825 const int CC2 = 1 << 1; local
839 case NE: return CC1 | CC2 | CC3;
848 case NE: return CC0 | CC2 | CC3;
856 case EQ: return CC2;
866 case NE: return CC0 | CC1 | CC2;
874 case EQ: return CC0 | CC2;
883 case LTU: return CC2 | CC3; /* carry */
893 case LEU: return CC2 | CC
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); local
485 if (CC1 == CC2)
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3694 AArch64CC::CondCode CC1, CC2; local
3695 changeFPCCToAArch64CC(CC, CC1, CC2);
3699 if (CC2 != AArch64CC::AL) {
3700 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3863 AArch64CC::CondCode CC1, CC2; local
3864 changeFPCCToAArch64CC(CC, CC1, CC2);
3865 if (CC2 == AArch64CC::AL) {
3866 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2); local
3884 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
4014 AArch64CC::CondCode CC1, CC2; local
6700 AArch64CC::CondCode CC1, CC2; local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1866 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1874 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1879 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1896 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1926 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1928 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1930 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1932 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
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