Searched refs:AR_BEACON (Results 1 - 17 of 17) sorted by relevance
| /freebsd-11.0-release/sys/dev/ath/ath_hal/ar5210/ |
| H A D | ar5210_beacon.c | 54 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
104 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
156 OS_REG_WRITE(ah, AR_BEACON,
157 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
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| H A D | ar5210_reset.c | 274 * Writing to AR_BEACON will start timers. Hence it should be
279 OS_REG_WRITE(ah, AR_BEACON,
280 (OS_REG_READ(ah, AR_BEACON) &
466 regBeacon = OS_REG_READ(ah, AR_BEACON);
467 OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN);
563 OS_REG_WRITE(ah, AR_BEACON, regBeacon);
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| H A D | ar5210_misc.c | 371 uint32_t val = OS_REG_READ(ah, AR_BEACON);
373 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
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| H A D | ar5210reg.h | 77 #define AR_BEACON 0x8024 /* Beacon control */ macro
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| /freebsd-11.0-release/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211_beacon.c | 57 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
113 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
161 OS_REG_WRITE(ah, AR_BEACON,
162 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
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| H A D | ar5211_misc.c | 367 uint32_t val = OS_REG_READ(ah, AR_BEACON);
369 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
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| H A D | ar5211_reset.c | 521 * Writing to AR_BEACON will start timers. Hence it should
526 OS_REG_WRITE(ah, AR_BEACON,
527 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
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| H A D | ar5211reg.h | 246 #define AR_BEACON 0x8020 /* beacon control value/mode bits */ macro
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| /freebsd-11.0-release/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212_beacon.c | 75 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
77 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
137 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
184 OS_REG_WRITE(ah, AR_BEACON,
185 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
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| H A D | ar5212_misc.c | 280 uint32_t val = OS_REG_READ(ah, AR_BEACON);
282 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
290 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
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| H A D | ar5212_reset.c | 76 ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \
180 * bit in the AR_BEACON register; it also has the quirk
597 * Writing to AR_BEACON will start timers. Hence it should
602 OS_REG_WRITE(ah, AR_BEACON,
603 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
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| H A D | ar5212reg.h | 261 #define AR_BEACON 0x8020 /* MAC beacon control value/mode bits */ macro
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| /freebsd-11.0-release/tools/tools/ath/common/ |
| H A D | dumpregs_5210.c | 82 DEFBASICfmt(AR_BEACON, "BEACON", AR_BEACON_BITS),
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| H A D | dumpregs_5211.c | 245 DEFBASICfmt(AR_BEACON, "BEACON", AR_BEACON_BITS),
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| H A D | dumpregs_5212.c | 283 DEFBASIC(AR_BEACON, "BEACON"),
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| H A D | dumpregs_5416.c | 319 DEFBASIC(AR_BEACON, "BEACON"),
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| /freebsd-11.0-release/sys/dev/ath/ath_hal/ar5312/ |
| H A D | ar5312_reset.c | 60 ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \
143 * bit in the AR_BEACON register; it also has the quirk
521 * Writing to AR_BEACON will start timers. Hence it should
526 OS_REG_WRITE(ah, AR_BEACON,
527 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
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