/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 416 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 417 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 420 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 421 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 466 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 470 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 474 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 499 { ISD::SRL, MVT::v8i16, 1286 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, member in class:MVT 1294 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, member in class:MVT [all...] |
H A D | X86ISelLowering.cpp | 869 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass 895 setOperationAction(ISD::MULHU, MVT::v8i16, Legal); 896 setOperationAction(ISD::MULHS, MVT::v8i16, Legal); 897 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 902 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { 903 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom); 904 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom); 913 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal); 914 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal); 915 setOperationAction(ISD::USUBSAT, MVT::v8i16, Lega [all...] |
H A D | X86InterleavedAccess.cpp | 326 MVT VT = MVT::v8i16;
|
H A D | X86FastISel.cpp | 392 case MVT::v8i16: 566 case MVT::v8i16: 2626 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16);
|
H A D | X86ISelDAGToDAG.cpp | 4023 case MVT::v8i16: 4070 case MVT::v8i16: 4100 case MVT::v8i16: 4147 case MVT::v8i16:
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 204 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0}, 205 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0}, 233 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, 234 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, 258 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 259 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 287 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, 288 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, 365 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 366 { ISD::ZERO_EXTEND, MVT::v8i16, MV [all...] |
H A D | ARMISelLowering.cpp | 254 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 }; 378 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal); 382 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16. 387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal); 392 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal); 767 addQRTypeForNEON(MVT::v8i16); 852 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 865 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom); 867 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); 869 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custo [all...] |
H A D | ARMISelDAGToDAG.cpp | 1752 (CanChangeType || LoadedVT == MVT::v8i16 || 2040 case MVT::v8i16: OpcodeIndex = 1; break; 2182 case MVT::v8i16: OpcodeIndex = 1; break; 2347 case MVT::v8i16: OpcodeIndex = 0; break; 2725 case MVT::v8i16: 3672 case MVT::v8i16: Opc = ARM::VZIPq16; break; 3695 case MVT::v8i16: Opc = ARM::VUZPq16; break; 3717 case MVT::v8i16: Opc = ARM::VTRNq16; break;
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
H A D | WebAssemblyMCTargetDesc.cpp | 144 case MVT::v8i16:
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 607 case MVT::v8i16: 1851 // Example: v8i16 -> v4i16 means the extract must begin at index 4. 3191 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { 3218 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { 3245 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { 3272 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { 3299 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { 3326 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { 3353 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { 3380 } else if (VT == MVT::v8i16 || V [all...] |
H A D | AArch64TargetTransformInfo.cpp | 314 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 315 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 318 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, 319 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, 349 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 351 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 946 {ISD::ADD, MVT::v8i16, 1}, member in class:MVT 965 { TTI::SK_Broadcast, MVT::v8i16, 1 }, 977 { TTI::SK_Transpose, MVT::v8i16, 1 },
|
H A D | AArch64ISelLowering.cpp | 147 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); 160 addQRTypeForNEON(MVT::v8i16); 759 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom); 760 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); 766 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i16, MVT::v8i32); 767 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i16, MVT::v8i32); 776 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 781 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { 808 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) { 1159 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) { [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 86 v8i16 = 38, // 8 x i16 351 SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 || 464 case v8i16: 600 case v8i16: 760 case v8i16: 951 if (NumElements == 8) return MVT::v8i16;
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 61 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); 119 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 129 for (auto T : {MVT::v16i8, MVT::v8i16}) 133 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 140 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 148 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 156 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 168 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 178 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 187 for (auto T : {MVT::v16i8, MVT::v8i16, MV [all...] |
H A D | WebAssemblyFastISel.cpp | 137 case MVT::v8i16: 685 case MVT::v8i16: 797 case MVT::v8i16: 1326 case MVT::v8i16:
|
H A D | WebAssemblyAsmPrinter.cpp | 60 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 705 for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8}) 743 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8}) 751 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); 767 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 774 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 793 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); 797 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal); 967 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal); 974 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 3368 ArgVT == MVT::v8i16 || ArgV [all...] |
H A D | PPCTargetTransformInfo.cpp | 861 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
|
H A D | PPCISelDAGToDAG.cpp | 3924 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32). 3999 else if (VecVT == MVT::v8i16) 4009 else if (VecVT == MVT::v8i16) 4019 else if (VecVT == MVT::v8i16) 5240 VT = MVT::v8i16;
|
/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/ |
H A D | msa.h | 18 typedef short v8i16 __attribute__((vector_size(16), aligned(16))); typedef
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 183 case MVT::v8i16: return VectorType::get(Type::getInt16Ty(Context), 8);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 274 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 352 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
|
H A D | MipsSEISelDAGToDAG.cpp | 1008 ViaVecTy = MVT::v8i16;
|
H A D | MipsSEISelLowering.cpp | 119 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); 2495 ViaVecTy = MVT::v8i16; 2931 // if the type is v8i16 and all the indices are less than 8 then the second
|
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 103 case MVT::v8i16: return "MVT::v8i16";
|