/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 424 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 425 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 428 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 429 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 440 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 442 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 467 { ISD::SHL, MVT::v4i32, 1 }, // pslld 471 { ISD::SRL, MVT::v4i32, [all...] |
H A D | X86ISelLowering.cpp | 871 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass 889 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 891 setOperationAction(ISD::MULHU, MVT::v4i32, Custom); 892 setOperationAction(ISD::MULHS, MVT::v4i32, Custom); 902 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { 917 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom); 918 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom); 923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 926 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { 939 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 200 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0}, 201 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0}, 202 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0}, 203 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0}, 219 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 220 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 223 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 224 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 243 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 244 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, [all...] |
H A D | ARMISelLowering.cpp | 230 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 254 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 }; 377 // It is legal to extload from v4i8 to v4i16 or v4i32. 379 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal); 380 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal); 382 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16. 385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); 390 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal); 391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal); 768 addQRTypeForNEON(MVT::v4i32); [all...] |
H A D | ARMISelDAGToDAG.cpp | 1747 (CanChangeType || LoadedVT == MVT::v4i32 || 2042 case MVT::v4i32: OpcodeIndex = 2; break; 2184 case MVT::v4i32: OpcodeIndex = 2; break; 2349 case MVT::v4i32: OpcodeIndex = 1; break; 2732 case MVT::v4i32: OpcodeIndex = 2; break; 3674 case MVT::v4i32: Opc = ARM::VZIPq32; break; 3697 case MVT::v4i32: Opc = ARM::VUZPq32; break; 3719 case MVT::v4i32: Opc = ARM::VTRNq32; break;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 302 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 303 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 310 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 311 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 327 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 330 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 368 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 371 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 947 {ISD::ADD, MVT::v4i32, 1}, member in class:MVT 967 { TTI::SK_Broadcast, MVT::v4i32, [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 613 case MVT::v4i32: 642 case MVT::v4i32: 653 case MVT::v4i32: 3197 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3224 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3251 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3278 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3305 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3332 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3359 } else if (VT == MVT::v4i32 || V [all...] |
H A D | AArch64ISelLowering.cpp | 161 addQRTypeForNEON(MVT::v4i32); 741 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32); 742 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32); 752 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16 753 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom); 754 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom); 764 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i16, MVT::v4i32); 765 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i16, MVT::v4i32); 777 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 781 MVT::v16i8, MVT::v8i16, MVT::v4i32, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
H A D | WebAssemblyMCTargetDesc.cpp | 145 case MVT::v4i32:
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 95 v4i32 = 46, // 4 x i32 351 SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 || 478 case v4i32: 619 case v4i32: 761 case v4i32: 961 if (NumElements == 4) return MVT::v4i32;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 62 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); 119 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 133 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 140 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 148 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 156 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 168 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 178 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 187 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 251 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MV [all...] |
H A D | WebAssemblyFastISel.cpp | 138 case MVT::v4i32: 689 case MVT::v4i32: 802 case MVT::v4i32: 1327 case MVT::v4i32:
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H A D | WebAssemblyAsmPrinter.cpp | 61 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 634 // We promote all non-typed operations to v4i32. 636 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 638 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 640 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 642 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 644 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 647 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); 649 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 697 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand); 705 for (auto VT : {MVT::v2i64, MVT::v4i32, MV [all...] |
H A D | PPCTargetTransformInfo.cpp | 862 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 64 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); 74 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); 97 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); 98 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); 99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); 104 setOperationAction(ISD::STORE, MVT::v4i32, Custom); 111 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom); 116 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); 123 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); 147 setOperationAction(ISD::SETCC, MVT::v4i32, Expan [all...] |
H A D | AMDGPUISelLowering.cpp | 80 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); 98 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32); 104 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32); 180 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); 198 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32); 204 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32); 280 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 291 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); 357 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32 445 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32); [all...] |
H A D | SIISelLowering.cpp | 138 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass); 178 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); 187 setOperationAction(ISD::STORE, MVT::v4i32, Custom); 196 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand); 201 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand); 292 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32. 295 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32); 298 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); 301 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); 304 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 973 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then 1012 ViaVecTy = MVT::v4i32; 1080 CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0)); 1181 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, 1185 Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
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H A D | MipsSEInstrInfo.cpp | 277 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 355 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
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H A D | MipsSEISelLowering.cpp | 120 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); 355 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { 1398 ViaVecTy = MVT::v4i32; 1436 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's. 1437 ViaVecTy = MVT::v4i32; 1486 DAG.getBuildVector(MVT::v4i32, DL, 1887 // an equivalent v4i32. 2498 ViaVecTy = MVT::v4i32;
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/ |
H A D | msa.h | 22 typedef int v4i32 __attribute__((vector_size(16), aligned(16))); typedef
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 191 case MVT::v4i32: return VectorType::get(Type::getInt32Ty(Context), 4);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 106 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass); 419 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 421 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); 423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); 428 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal); 430 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal); 432 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal); 434 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal); 1377 case MVT::v4i32 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 111 case MVT::v4i32: return "MVT::v4i32";
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