Searched refs:v4f32 (Results 1 - 25 of 29) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp187 { ISD::FDIV, MVT::v4f32, 35 }, // divps
203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps
205 { ISD::FDIV, MVT::v4f32, 39 }, // divps
703 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
740 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
760 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
765 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
768 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
833 { ISD::FDIV, MVT::v4f32, 3
[all...]
H A DX86ISelLowering.cpp755 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
839 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
842 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
843 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
844 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
845 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
846 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
847 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
848 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::SELECT, MVT::v4f32, Custo
[all...]
H A DX86FastISel.cpp368 case MVT::v4f32:
540 case MVT::v4f32:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp327 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
330 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
341 // Complex: to v4f32
342 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
343 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
344 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
345 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
368 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
371 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
382 // Complex, from v4f32
[all...]
H A DAArch64ISelDAGToDAG.cpp1842 (VT != MVT::v4f32 || NarrowVT != MVT::v4f16))
3197 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3224 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3251 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3278 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3305 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3332 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3359 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3386 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3413 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
[all...]
H A DAArch64ISelLowering.cpp157 addQRTypeForNEON(MVT::v4f32);
457 // promote v4f16 to v4f32 when that is known to be safe.
462 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
463 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
464 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
465 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
752 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
796 MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
830 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
878 if (VT == MVT::v2f32 || VT == MVT::v4f32 || V
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp163 { ISD::FP_EXTEND, MVT::v4f32, 4 }
243 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
244 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
253 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
254 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
255 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
256 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
257 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
267 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32,
[all...]
H A DARMISelLowering.cpp313 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
764 addQRTypeForNEON(MVT::v4f32);
816 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
817 // supported for v4f32.
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
819 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
820 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
821 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
822 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
823 setOperationAction(ISD::FLOG2, MVT::v4f32, Expan
[all...]
H A DARMISelDAGToDAG.cpp1748 LoadedVT == MVT::v4f32) &&
2041 case MVT::v4f32:
2183 case MVT::v4f32:
2348 case MVT::v4f32:
2731 case MVT::v4f32:
3673 case MVT::v4f32:
3696 case MVT::v4f32:
3718 case MVT::v4f32:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.cpp147 case MVT::v4f32:
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h128 v4f32 = 73, // 4 x f32
353 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v4f32 ||
520 case v4f32:
622 case v4f32:
765 case v4f32:
996 if (NumElements == 4) return MVT::v4f32;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp731 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
732 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
733 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
734 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
749 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
754 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
755 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
758 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
759 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
770 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custo
[all...]
H A DPPCTargetTransformInfo.cpp862 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
866 (LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
H A DPPCISelDAGToDAG.cpp3924 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
3953 if (VecVT == MVT::v4f32)
3960 if (VecVT == MVT::v4f32)
3967 if (VecVT == MVT::v4f32)
4697 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
4975 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp108 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
334 // as such. In particular, we can do these for v4f32 even though there
420 setOperationAction(ISD::FP_TO_SINT, MVT::v4f32, Legal);
422 setOperationAction(ISD::FP_TO_UINT, MVT::v4f32, Legal);
424 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal);
426 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal);
429 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4f32, Legal);
431 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4f32, Legal);
433 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4f32, Legal);
435 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4f32, Lega
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp63 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
85 for (auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
133 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
140 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
156 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
168 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
195 setOperationAction(Op, MVT::v4f32, Expand);
207 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
208 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
251 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32,
[all...]
H A DWebAssemblyFastISel.cpp139 case MVT::v4f32:
697 case MVT::v4f32:
812 case MVT::v4f32:
1329 case MVT::v4f32:
H A DWebAssemblyAsmPrinter.cpp61 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp79 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
80 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
155 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
162 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
179 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
180 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
219 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
230 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
281 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
290 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custo
[all...]
H A DR600ISelLowering.cpp63 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass);
212 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
217 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
569 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
1475 // non-constant ptr can't be folded, keeps it as a v4f32 load
/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/
H A Dmsa.h30 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp218 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp278 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
356 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp151 case MVT::v4f32:
456 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
458 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
2314 case MVT::v4f32:
3885 Info.memVT = MVT::v4f32;
4805 case MVT::v4f32:
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp138 case MVT::v4f32: return "MVT::v4f32";

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