Searched refs:v2f64 (Results 1 - 25 of 29) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp328 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
331 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
357 // Complex: to v2f64
358 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
359 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
360 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
361 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
362 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
363 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
369 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64,
[all...]
H A DAArch64ISelDAGToDAG.cpp1841 if ((VT != MVT::v2f64 || NarrowVT != MVT::v2f32) &&
1856 auto Opcode = VT == MVT::v2f64 ? AArch64::FCVTLv4i32 : AArch64::FCVTLv8i16;
3203 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3230 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3257 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3284 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3311 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3338 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3365 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3392 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
[all...]
H A DAArch64ISelLowering.cpp158 addQRTypeForNEON(MVT::v2f64);
796 MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
830 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
878 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
5115 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
5136 if (VT == MVT::f64 || VT == MVT::v2f64) {
5137 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
5138 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
6039 (VT == MVT::f64 || VT == MVT::v1f64 || VT == MVT::v2f64 ||
7266 // dup (bitcast (extract_subv v2f64
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp30 // For the 2nd half of a v2f64, do not fail.
57 if (LocVT == MVT::v2f64 &&
79 // For the 2nd half of a v2f64, do not just fail.
111 if (LocVT == MVT::v2f64 &&
143 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
222 case MVT::v2f64:
H A DARMTargetTransformInfo.cpp161 { ISD::FP_ROUND, MVT::v2f64, 2 },
275 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
276 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
278 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
279 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
280 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
281 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
282 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
283 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
285 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64,
[all...]
H A DARMISelLowering.cpp230 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
364 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
765 addQRTypeForNEON(MVT::v2f64);
778 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
780 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
781 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
782 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
785 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
786 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
790 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expan
[all...]
H A DARMISelDAGToDAG.cpp2043 case MVT::v2f64:
2185 case MVT::v2f64:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd
207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd
208 { ISD::FADD, MVT::v2f64, 2 }, // addpd
209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd
706 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
743 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/
754 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
759 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
764 { ISD::FMUL, MVT::v2f64,
[all...]
H A DX86ISelLowering.cpp756 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
862 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
898 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
899 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
900 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
947 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
959 // Custom lower v2i64 and v2f64 selects.
960 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1045 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1046 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Lega
[all...]
H A DX86FastISel.cpp379 case MVT::v2f64:
552 case MVT::v2f64:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.cpp148 case MVT::v2f64:
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h140 v2f64 = 85, // 2 x f64
354 SimpleTy == MVT::v2f64);
537 case v2f64:
643 case v2f64:
766 case v2f64: return TypeSize::Fixed(128);
1010 if (NumElements == 2) return MVT::v2f64;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp109 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
397 // There should be no need to check for float types other than v2f64
400 setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Legal);
402 setOperationAction(ISD::FP_TO_UINT, MVT::v2f64, Legal);
404 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal);
406 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal);
409 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f64, Legal);
411 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f64, Legal);
413 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f64, Legal);
415 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f64, Lega
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp785 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
801 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
810 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
811 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
812 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
813 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
814 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
821 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMA, MVT::v2f64, Lega
[all...]
H A DPPCTargetTransformInfo.cpp864 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
H A DPPCISelDAGToDAG.cpp3955 else if (VecVT == MVT::v2f64)
3962 else if (VecVT == MVT::v2f64)
3969 else if (VecVT == MVT::v2f64)
4979 else if (N->getValueType(0) == MVT::v2f64 ||
4991 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp67 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
85 for (auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
136 for (auto T : {MVT::v2i64, MVT::v2f64})
143 for (auto T: {MVT::v2i64, MVT::v2f64})
159 for (auto T : {MVT::v2i64, MVT::v2f64})
171 for (auto T : {MVT::v2i64, MVT::v2f64})
197 setOperationAction(Op, MVT::v2f64, Expand);
252 MVT::v2f64}) {
H A DWebAssemblyFastISel.cpp144 case MVT::v2f64:
701 case MVT::v2f64:
817 case MVT::v2f64:
1330 case MVT::v2f64:
H A DWebAssemblyAsmPrinter.cpp61 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/
H A Dmsa.h32 typedef double v2f64 __attribute__ ((vector_size(16), aligned(16))); typedef
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp230 case MVT::v2f64: return VectorType::get(Type::getDoubleTy(Context), 2);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp281 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
359 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp103 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
104 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
161 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
166 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
203 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
204 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
227 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
228 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp150 case MVT::v2f64: return "MVT::v2f64";
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp152 case MVT::v2f64:
454 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
455 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
2309 case MVT::v2f64:
4800 case MVT::v2f64:

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