/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 332 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 333 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 408 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 409 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 412 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 413 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 516 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i8, 1287 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, member in class:MVT 1295 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, member in class:MVT [all...] |
H A D | X86ISelLowering.cpp | 867 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass 888 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 893 setOperationAction(ISD::MULHU, MVT::v16i8, Custom); 894 setOperationAction(ISD::MULHS, MVT::v16i8, Custom); 902 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { 905 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom); 906 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom); 909 setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal); 910 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal); 911 setOperationAction(ISD::USUBSAT, MVT::v16i8, Lega [all...] |
H A D | X86InterleavedAccess.cpp | 416 if (VT == MVT::v16i8) {
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H A D | X86ISelDAGToDAG.cpp | 4021 case MVT::v16i8: 4068 case MVT::v16i8: 4098 case MVT::v16i8: 4145 case MVT::v16i8: 5208 CNode = emitPCMPISTR(ROpc, MOpc, MayFoldLoad, dl, MVT::v16i8, Node); 5243 CNode = emitPCMPESTR(ROpc, MOpc, MayFoldLoad, dl, MVT::v16i8, Node,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
H A D | WebAssemblyMCTargetDesc.cpp | 143 case MVT::v16i8:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 3185 } else if (VT == MVT::v16i8) { 3212 } else if (VT == MVT::v16i8) { 3239 } else if (VT == MVT::v16i8) { 3266 } else if (VT == MVT::v16i8) { 3293 } else if (VT == MVT::v16i8) { 3320 } else if (VT == MVT::v16i8) { 3347 } else if (VT == MVT::v16i8) { 3374 } else if (VT == MVT::v16i8) { 3401 } else if (VT == MVT::v16i8) { 3425 if (VT == MVT::v16i8 || V [all...] |
H A D | AArch64TargetTransformInfo.cpp | 305 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 320 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 321 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 322 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 323 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 354 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, 355 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, 944 {ISD::ADD, MVT::v16i8, 1}, member in class:MVT 963 { TTI::SK_Broadcast, MVT::v16i8, 1 }, 975 { TTI::SK_Transpose, MVT::v16i8, [all...] |
H A D | AArch64ISelLowering.cpp | 146 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); 159 addQRTypeForNEON(MVT::v16i8); 781 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { 808 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) { 911 if (VT != MVT::v8i8 && VT != MVT::v16i8) 1155 if (VT == MVT::v8i8 || VT == MVT::v16i8) { 5194 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; 5198 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds. 7155 IndexVT = MVT::v16i8; 7165 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cs [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 235 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 236 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 239 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 591 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}; 613 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}}; 638 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}}; 652 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}, 716 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, 717 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, 718 { ISD::SREM, MVT::v16i8, 1 [all...] |
H A D | ARMISelDAGToDAG.cpp | 1756 else if ((CanChangeType || LoadedVT == MVT::v16i8) && 2038 case MVT::v16i8: OpcodeIndex = 0; break; 2180 case MVT::v16i8: OpcodeIndex = 0; break; 2723 case MVT::v16i8: OpcodeIndex = 0; break; 3670 case MVT::v16i8: Opc = ARM::VZIPq8; break; 3693 case MVT::v16i8: Opc = ARM::VUZPq8; break; 3715 case MVT::v16i8: Opc = ARM::VTRNq8; break;
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H A D | ARMISelLowering.cpp | 254 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 }; 766 addQRTypeForNEON(MVT::v16i8); 878 // v8i8/v16i8 vcnt instruction. 895 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); 905 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom); 1527 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1720 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8)) 6013 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; 6017 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds. 6448 VT = is128Bits ? MVT::v16i8 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 76 v16i8 = 29, // 16 x i8 350 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 || 449 case v16i8: 586 case v16i8: 759 case v16i8: 940 if (NumElements == 16) return MVT::v16i8;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 60 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); 119 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 129 for (auto T : {MVT::v16i8, MVT::v8i16}) 133 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 140 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 148 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 156 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 168 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) 178 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) 187 for (auto T : {MVT::v16i8, MV [all...] |
H A D | WebAssemblyFastISel.cpp | 136 case MVT::v16i8: 681 case MVT::v16i8: 792 case MVT::v16i8: 1325 case MVT::v16i8:
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H A D | WebAssemblyAsmPrinter.cpp | 60 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
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H A D | WebAssemblyExplicitLocals.cpp | 161 return MVT::v16i8;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 630 // We promote all shuffles to v16i8. 632 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 705 for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8}) 710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 743 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8}) 752 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); 768 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 773 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 792 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); 796 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Lega 2058 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); member in class:MVT [all...] |
H A D | PPCTargetTransformInfo.cpp | 861 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
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H A D | PPCISelDAGToDAG.cpp | 3924 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32). 3997 if (VecVT == MVT::v16i8) 4007 if (VecVT == MVT::v16i8) 4017 if (VecVT == MVT::v16i8) 5235 VT = MVT::v16i8;
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/ |
H A D | msa.h | 14 typedef signed char v16i8 __attribute__((vector_size(16), aligned(16))); typedef
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 174 case MVT::v16i8: return VectorType::get(Type::getInt8Ty(Context), 16);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 272 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 350 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
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H A D | MipsSEISelDAGToDAG.cpp | 1004 ViaVecTy = MVT::v16i8;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 104 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass); 1375 case MVT::v16i8: 3712 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op); 3713 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op); 3726 SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL, 3732 SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL, 4430 Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]); 4435 return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0], 4446 SDValue Op2 = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes); 4447 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Op [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 94 case MVT::v16i8: return "MVT::v16i8";
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