Searched refs:target_clock (Results 1 - 4 of 4) sorted by relevance

/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_display.c749 u32 target_clock,
757 tmp *= target_clock;
768 u32 target_clock)
787 post_div = vco / target_clock;
788 tmp = vco % target_clock;
816 u32 target_clock = freq / 10; local
817 u32 post_div = avivo_get_post_div(pll, target_clock);
825 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
838 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
844 tmp = (tmp * 10000) / target_clock;
748 avivo_get_fb_div(struct radeon_pll *pll, u32 target_clock, u32 post_div, u32 ref_div, u32 *fb_div, u32 *frac_fb_div) argument
767 avivo_get_post_div(struct radeon_pll *pll, u32 target_clock) argument
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/freebsd-11-stable/sys/dev/drm2/i915/
H A Dintel_dp.c780 int target_clock; local
796 target_clock = mode->clock;
799 target_clock = intel_edp_target_clock(intel_encoder,
811 target_clock, adjusted_mode->clock, &m_n);
H A Dintel_drv.h588 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
H A Dintel_display.c5402 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) argument
5409 u32 bps = target_clock * bpp * 21 / 20;
5423 int target_clock, pixel_multiplier, lane, link_bw; local
5460 target_clock = intel_edp_target_clock(edp_encoder, mode);
5462 target_clock = mode->clock;
5464 target_clock = adjusted_mode->clock;
5467 lane = ironlake_get_lanes_required(target_clock, link_bw,
5474 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,

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