Searched refs:sclk (Results 1 - 13 of 13) sorted by relevance

/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_pm.c164 u32 sclk, mclk; local
172 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
173 clock_info[rdev->pm.requested_clock_mode_index].sclk;
174 if (sclk > rdev->pm.default_sclk)
175 sclk = rdev->pm.default_sclk;
196 if (sclk < rdev->pm.current_sclk)
213 if (sclk != rdev->pm.current_sclk) {
215 radeon_set_engine_clock(rdev, sclk);
217 rdev->pm.current_sclk = sclk;
218 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
[all...]
H A Dradeon_atombios.c2062 rdev->pm.power_state[state_index].clock_info[0].sclk =
2066 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2097 rdev->pm.power_state[state_index].clock_info[0].sclk =
2101 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2133 rdev->pm.power_state[state_index].clock_info[0].sclk =
2137 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2330 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2339 rdev->pm.power_state[state_index].clock_info[j].sclk =
2353 u32 sclk, mclk; local
2358 sclk
[all...]
H A Drs690.c228 fixed20_12 sclk; member in struct:rs690_watermark
326 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
328 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
330 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
334 * sclk = system clock(ns)
337 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
459 fill_rate.full = dfixed_div(wm0.sclk, a);
507 fill_rate.full = dfixed_div(wm0.sclk, a);
534 fill_rate.full = dfixed_div(wm1.sclk,
[all...]
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; local
56 sclk = fb_div / ref_div;
60 sclk >>= 1;
62 sclk >>= 2;
64 sclk >>= 3;
66 return sclk;
H A Dradeon_device.c486 * Used when sclk/mclk are switched or display modes are set.
492 u32 sclk = rdev->pm.current_sclk; local
495 /* sclk/mclk in Mhz */
497 rdev->pm.sclk.full = dfixed_const(sclk);
498 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
504 /* core_bandwidth = sclk(Mhz) * 16 */
505 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
H A Dradeon_i2c.c314 u32 sclk = rdev->pm.current_sclk; local
334 nm = (sclk * 10) / (i2c_clock * 4);
349 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
364 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
366 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
414 /* take the pm lock since we need a constant sclk */
666 /* take the pm lock since we need a constant sclk */
H A Dsi.c535 u32 sclk; /* engine clock in kHz */ member in struct:dce6_wm_params
592 fixed20_12 sclk, bandwidth; local
596 sclk.full = dfixed_const(wm->sclk);
597 sclk.full = dfixed_div(sclk, a);
602 bandwidth.full = dfixed_mul(a, sclk);
617 fixed20_12 disp_clk, sclk, bandwidth; local
628 sclk.full = dfixed_const(wm->sclk);
[all...]
H A Drv515.c937 fixed20_12 sclk; member in struct:rv515_watermark
1017 * sclk = system clock(Mhz)
1020 chunk_time.full = dfixed_div(a, rdev->pm.sclk);
1116 fill_rate.full = dfixed_div(wm0.sclk, a);
1164 fill_rate.full = dfixed_div(wm0.sclk, a);
1191 fill_rate.full = dfixed_div(wm1.sclk, a);
H A Dradeon_combios.c825 uint16_t sclk, mclk; local
878 /* default sclk/mclk */
879 sclk = RBIOS16(pll_info + 0xa);
881 if (sclk == 0)
882 sclk = 200 * 100;
886 rdev->clock.default_sclk = sclk;
2818 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2820 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2892 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
H A Devergreen.c825 u32 sclk; /* engine clock in kHz */ member in struct:evergreen_wm_params
882 fixed20_12 sclk, bandwidth; local
886 sclk.full = dfixed_const(wm->sclk);
887 sclk.full = dfixed_div(sclk, a);
892 bandwidth.full = dfixed_mul(a, sclk);
1072 wm.sclk = rdev->pm.current_sclk * 10;
1092 /* wm.yclk = low clk; wm.sclk = low clk */
H A Dradeon.h939 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1021 u32 delay; /* delay in usec from voltage drop to sclk change */
1040 u32 sclk; member in struct:radeon_pm_clock_info
1085 fixed20_12 sclk; member in struct:radeon_pm
H A Dr100.c298 clock_info[rdev->pm.requested_clock_mode_index].sclk,
3354 sclk_ff = rdev->pm.sclk;
H A Dr600.c290 clock_info[rdev->pm.requested_clock_mode_index].sclk,

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