Searched refs:pclk (Results 1 - 5 of 5) sorted by relevance

/freebsd-11-stable/sys/arm/nvidia/drm2/
H A Dtegra_drm.h82 clk_t clk, uint64_t pclk);
H A Dtegra_hdmi.c131 uint32_t pclk; member in struct:tmds_config
143 .pclk = 27000000,
152 .pclk = 74250000,
161 .pclk = 148500000,
170 .pclk = UINT_MAX,
194 uint64_t pclk; member in struct:hdmi_softc
262 hdmi_setup_clock(struct tegra_drm_encoder *output, clk_t clk, uint64_t pclk) argument
283 freq = HDMI_DC_CLOCK_MULTIPIER * pclk;
304 rv = clk_set_freq(sc->clk_hdmi, pclk, 0);
770 sc->pclk
[all...]
H A Dtegra_dc.c320 uint64_t pclk, freq; local
325 pclk = mode->clock * 1000;
342 rv = output->setup_clock(output, sc->clk_dc, pclk);
345 pclk);
350 *div = (freq * 2 / pclk) - 2;
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Drs690.c237 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; local
263 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
271 pclk.full = dfixed_div(b, a);
279 consumption_time.full = dfixed_div(pclk, b);
281 consumption_time.full = pclk.full;
290 * pclk = pixel clock period(ns)
293 line_time.full = dfixed_mul(a, pclk);
H A Drv515.c946 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; local
972 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
980 pclk.full = dfixed_div(b, a);
988 consumption_time.full = dfixed_div(pclk, b);
990 consumption_time.full = pclk.full;
999 * pclk = pixel clock period(ns)
1002 line_time.full = dfixed_mul(a, pclk);

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