Searched refs:isPredicated (Results 1 - 25 of 38) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
213 CantAnalyze = !isPredicated(*I);
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) ||
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp360 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
562 if (!HII->isPredicated(MI))
693 if (HII->isPredicated(PacketMI)) {
694 if (!HII->isPredicated(MI))
918 if (!HII->isPredicated(*I))
945 assert(QII->isPredicated(MI) && "Must be predicated instruction");
1200 if (HII->isPredicated(I) || HII->isPredicated(J))
1240 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1461 if (HII->isPredicated(
[all...]
H A DHexagonExpandCondsets.cpp343 if (HII->isPredicated(*DefI))
421 if (HII->isPredicated(*DefI))
491 if (!HII->isPredicated(*DefI))
723 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
758 if (PredValid && HII->isPredicated(*MI)) {
916 if (!HII->isPredicated(*MI))
989 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
H A DHexagonInstrInfo.h222 bool isPredicated(const MachineInstr &MI) const override;
387 bool isPredicated(unsigned Opcode) const;
H A DHexagonPeephole.cpp238 if (QII->isPredicated(MI)) {
H A DHexagonInstrInfo.cpp605 if (Term != MBB.end() && isPredicated(*Term) &&
1557 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const { function in class:HexagonInstrInfo
2135 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2419 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2442 assert(isPredicated(MI));
2448 assert(isPredicated(Opcode));
2466 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { function in class:HexagonInstrInfo
3143 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3208 if (isPredicated(MI)) {
3675 if (isPredicated(NewO
[all...]
H A DHexagonNewValueJump.cpp124 if (QII->isPredicated(*II))
H A DHexagonConstExtenders.cpp1679 if (HII->isPredicated(MI))
1806 if (HII->isPredicated(MI))
1924 assert(HII->isPredicated(MI));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h266 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
300 bool isPredicated() const;
H A DHexagonMCInstrInfo.cpp34 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { function in class:HexagonMCInstrInfo::PredicateInfo
628 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, function in class:HexagonMCInstrInfo
818 if (!isPredicated(MCII, MCI))
H A DHexagonMCChecker.cpp68 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) {
425 if (std::get<2>(Producer).isPredicated() &&
426 (!Consumer.isPredicated() ||
H A DHexagonMCCodeEmitter.cpp763 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
767 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp183 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI);
258 if (!TII->isPredicated(MI)) {
614 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI))
H A DIfConversion.cpp1110 bool isPredicated = TII->isPredicated(MI); local
1122 if (!isPredicated) {
1137 if (BBI.ClobbersPred && !isPredicated) {
1992 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T);
1993 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T);
2084 if (TI != BBI.BB->end() && TII->isPredicated(*TI))
2142 if (I.isDebugInstr() || TII->isPredicated(I))
2202 if (!TII->isPredicated(I) && !MI->isDebugInstr()) {
2256 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromT
[all...]
H A DTargetSchedule.cpp306 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
H A DAggressiveAntiDepBreaker.cpp389 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
467 TII->isPredicated(MI) || MI.isInlineAsm();
H A DBranchFolding.cpp1910 if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(*PI))
1978 if (TII->isPredicated(*TIB))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h180 bool isPredicated(const MachineInstr &MI) const override;
H A DR600Packetizer.cpp84 if (TII->isPredicated(*BI))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp172 return !isPredicated(MI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp326 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
358 CantAnalyze = !isPredicated(*I);
366 if (!isPredicated(*I) &&
482 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const { function in class:ARMBaseInstrInfo
2890 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
2899 isPredicated(*PotentialAND))
3018 if (isPredicated(*MI))
3147 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
3165 if (isPredicated(MI))
4839 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(M
[all...]
H A DARMBaseInstrInfo.h147 bool isPredicated(const MachineInstr &MI) const override;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp926 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) {
1028 if ((isPredicated(BlockA) || isPredicated(BlockB)) &&
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h699 bool isPredicated(BasicBlock *BB) const { function in class:llvm::InterleavedAccessInfo
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h336 bool isPredicated(const MachineInstr &MI) const override;

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