/freebsd-11-stable/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/ |
H A D | tst.signedkeyspos.d | 82 @i32["mouse", -2] = sum(-2); 83 @i32["bear", -2] = sum(-22); 84 @i32["cat", -2] = sum(-222); 85 @i32["mouse", -1] = sum(-1); 86 @i32["bear", -1] = sum(-11); 87 @i32["cat", -1] = sum(-111); 88 @i32["mouse", 0] = sum(0); 89 @i32["bear", 0] = sum(10); 90 @i32["cat", 0] = sum(100); 91 @i32["mous [all...] |
H A D | tst.signedkeys.d | 107 @i32[-2] = sum(-2); 108 @i32[-1] = sum(-1); 109 @i32[0] = sum(0); 110 @i32[1] = sum(1); 111 @i32[2] = sum(2);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 48 /// i32. 50 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); 91 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 92 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); 101 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 103 MVT::i32); 120 Reg = CurDAG->getRegister(XCore::CP, MVT::i32); 123 Reg = CurDAG->getRegister(XCore::DP, MVT::i32); 143 MVT::i32, MskSize)); 150 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, [all...] |
H A D | XCoreISelLowering.cpp | 78 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); 87 // Use i32 for setcc operations results (slt, sgt, ...). 92 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 93 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 98 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 99 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 100 setOperationAction(ISD::MULHS, MVT::i32, Expand); 101 setOperationAction(ISD::MULHU, MVT::i32, Expand); 102 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 103 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expan [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySelectionDAGInfo.cpp | 30 SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32); 33 DAG.getZExtOrTrunc(Size, DL, MVT::i32)}); 54 SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32); 57 Dst, DAG.getAnyExtOrTrunc(Val, DL, MVT::i32), 58 DAG.getZExtOrTrunc(Size, DL, MVT::i32));
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H A D | WebAssemblyISelDAGToDAG.cpp | 114 CurDAG->getTargetConstant(0, DL, MVT::i32), // order 149 assert(PtrVT == MVT::i32 && "only wasm32 is supported for now"); 156 DL, MVT::i32, TLSBaseSym); 158 WebAssembly::CONST_I32, DL, MVT::i32, TLSOffsetSym); 160 CurDAG->getMachineNode(WebAssembly::ADD_I32, DL, MVT::i32, 171 assert(PtrVT == MVT::i32 && "only wasm32 is supported for now"); 175 CurDAG->getTargetExternalSymbol("__tls_size", MVT::i32)); 181 assert(PtrVT == MVT::i32 && "only wasm32 is supported for now"); 185 CurDAG->getTargetExternalSymbol("__tls_align", MVT::i32)); 197 assert(PtrVT == MVT::i32 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 77 addRegisterClass(MVT::i32, &Lanai::GPRRegClass); 85 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 88 setOperationAction(ISD::SETCC, MVT::i32, Custom); 89 setOperationAction(ISD::SELECT, MVT::i32, Expand); 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 92 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 93 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 94 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 95 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 97 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custo [all...] |
H A D | LanaiISelDAGToDAG.cpp | 84 // getI32Imm - Return a target constant with the specified value, of type i32. 86 return CurDAG->getTargetConstant(Imm, DL, MVT::i32); 133 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32); 146 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32); 157 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32); 158 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32); 170 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32); 185 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i32); 196 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32); 197 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelDAGToDAG.cpp | 53 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32); 54 Reg = CurDAG->getRegister(ARC::STATUS32, MVT::i32); 79 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); 101 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); 119 Offset = CurDAG->getTargetConstant(RHSC, SDLoc(Addr), MVT::i32); 123 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); 139 Offset = CurDAG->getTargetConstant(RHSC, SDLoc(Addr), MVT::i32); 150 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 151 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); 160 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); [all...] |
H A D | ARCISelLowering.cpp | 76 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); 85 // Use i32 for setcc operations results (slt, sgt, ...). 90 setOperationAction(Opc, MVT::i32, Expand); 94 setOperationAction(ISD::ADD, MVT::i32, Legal); 95 setOperationAction(ISD::SUB, MVT::i32, Legal); 96 setOperationAction(ISD::AND, MVT::i32, Legal); 97 setOperationAction(ISD::SMAX, MVT::i32, Legal); 98 setOperationAction(ISD::SMIN, MVT::i32, Legal); 101 setOperationAction(ISD::SHL, MVT::i32, Legal); 102 setOperationAction(ISD::SRA, MVT::i32, Lega [all...] |
/freebsd-11-stable/sys/i386/i386/ |
H A D | bpf_jit_machdep.h | 108 /* movl i32,r32 */ 109 #define MOVid(i32, r32) do { \ 111 emitm(&stream, i32, 4); \ 195 /* addl i32,%eax */ 196 #define ADD_EAXi(i32) do { \ 198 emitm(&stream, i32, 4); \ 215 /* subl i32,%eax */ 216 #define SUB_EAXi(i32) do { \ 218 emitm(&stream, i32, 4); \ 251 /* andl i32,r3 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 234 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32); 236 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32); 238 SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, 242 Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne); 245 CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne, 247 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops); 254 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32); 258 CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps); 748 MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32; 779 Mips::ZERO, MVT::i32); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 147 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); 171 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, CCReg); 172 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, 173 DAG.getConstant(30 - SystemZ::IPM_CC, DL, MVT::i32)); 174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, 175 DAG.getConstant(30, DL, MVT::i32)); 199 SDVTList VTs = DAG.getVTList(PtrVT, MVT::i32, MVT::Other); 201 Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32); 202 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char, 203 DAG.getConstant(255, DL, MVT::i32)); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 73 /// getI32Imm - Return a target constant of type i32 with the specified 76 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); 107 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32); 108 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); 243 /// 2 for long non-rounding variants, vml{a,s}ldav[a][x]: [i16, i32] 244 /// 1 for long rounding variants: vrml{a,s}ldavh[a][x]: [i32] 329 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 442 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, 445 MVT::i32)); 446 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32, [all...] |
H A D | ARMSelectionDAGInfo.cpp | 89 // Extend or truncate the argument to be an i32 value for the call. 90 if (Src.getValueType().bitsGT(MVT::i32)) 91 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 92 else if (Src.getValueType().bitsLT(MVT::i32)) 93 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 151 EVT VT = MVT::i32; 177 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other, MVT::Glue); 186 DAG.getConstant(NumRegs, dl, MVT::i32)); 213 DAG.getNode(ISD::ADD, dl, MVT::i32, Sr [all...] |
/freebsd-11-stable/sys/libkern/ |
H A D | murmur3_32.c | 34 #define rol32(i32, n) ((i32) << (n) | (i32) >> (32 - (n)))
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/freebsd-11-stable/sys/amd64/amd64/ |
H A D | bpf_jit_machdep.h | 133 /* movl i32,r32 */ 134 #define MOVid(i32, r32) do { \ 136 emitm(&stream, i32, 4); \ 250 /* addl i32,%eax */ 251 #define ADD_EAXi(i32) do { \ 253 emitm(&stream, i32, 4); \ 270 /* subl i32,%eax */ 271 #define SUB_EAXi(i32) do { \ 273 emitm(&stream, i32, 4); \ 306 /* andl i32,r3 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 80 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); 100 MVT::i32); 116 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); 243 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, 245 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, 262 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, 264 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, 271 MVT::i32), 273 CurDAG->getTargetConstant(SP::sub_even, dl, MVT::i32), 275 CurDAG->getTargetConstant(SP::sub_odd, dl, MVT::i32), [all...] |
H A D | SparcISelLowering.cpp | 164 if (LocVT == MVT::i32 && Offset < 6*8) { 170 // Set the Custom bit if this i32 goes in the high bits of a register. 241 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would 244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, 247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, 281 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32); 313 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32)); 337 // The custom bit on an i32 return value indicates that it should be passed 339 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 341 DAG.getConstant(32, DL, MVT::i32)); [all...] |
/freebsd-11-stable/tools/tools/shlib-compat/test/libtest3/ |
H A D | test.c | 37 typedef int i32; typedef 43 int32_t func5(i32 a, void *b, struct s2 *s);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 115 DAG.getTargetConstant(K, SL, MVT::i32)); 632 return glueCopyToM0(N, CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32)); 637 glueCopyToM0(N, CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i32)); 645 AMDGPU::S_MOV_B32, DL, MVT::i32, 646 CurDAG->getTargetConstant(Imm & 0xFFFFFFFF, DL, MVT::i32)); 648 CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, 649 CurDAG->getTargetConstant(Imm >> 32, DL, MVT::i32)); 651 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32), 652 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), 653 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)}; [all...] |
H A D | R600ISelLowering.cpp | 60 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); 72 setOperationAction(ISD::LOAD, MVT::i32, Custom); 102 setOperationAction(ISD::STORE, MVT::i32, Custom); 106 setTruncStoreAction(MVT::i32, MVT::i8, Custom); 107 setTruncStoreAction(MVT::i32, MVT::i16, Custom); 139 setCondCodeAction(ISD::SETLE, MVT::i32, Expand); 140 setCondCodeAction(ISD::SETLT, MVT::i32, Expand); 141 setCondCodeAction(ISD::SETULE, MVT::i32, Expand); 142 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); 150 setOperationAction(ISD::BR_CC, MVT::i32, Expan [all...] |
H A D | AMDGPUISelLowering.cpp | 48 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); 71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); 121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); 126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); 131 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); 171 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); 209 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 237 setOperationAction(ISD::Constant, MVT::i32, Legal); 246 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 305 const MVT ScalarIntVTs[] = { MVT::i32, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 211 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); 289 if (ElemIdx.getValueType().getSimpleVT() != MVT::i32) 290 ElemIdx = DAG.getBitcast(MVT::i32, ElemIdx); 298 return DAG.getNode(ISD::SHL, dl, MVT::i32, 299 {ElemIdx, DAG.getConstant(L, dl, MVT::i32)}); 310 if (ty(Idx) != MVT::i32) 311 Idx = DAG.getBitcast(MVT::i32, Idx); 313 SDValue Mask = DAG.getConstant(32/ElemWidth - 1, dl, MVT::i32); 314 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); 363 if (VecTy.getVectorElementType() != MVT::i32) { [all...] |
H A D | HexagonISelDAGToDAG.cpp | 95 case MVT::i32: 129 SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32); 135 SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32); 151 // A load extending to i64 will actually produce i32, which will then 154 ValueVT = MVT::i32; 159 MVT::i32, MVT::Other, Base, 169 SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32); 174 MachineSDNode *A = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32, 203 EVT ValTy = (IntNo == Intrinsic::hexagon_circ_ldd) ? MVT::i64 : MVT::i32; 204 EVT RTys[] = { ValTy, MVT::i32, MV [all...] |