/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86InstComments.cpp | 217 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); 240 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); 270 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 275 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 276 Mul1Name = getRegName(MI->getOperand(1).getReg()); 281 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); 286 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 287 Mul2Name = getRegName(MI->getOperand(1).getReg()); 292 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 297 Mul1Name = getRegName(MI->getOperand(NumOperand [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ClauseMergePass.cpp | 87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) 94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) 111 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); 136 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && 137 RootCFAlu.getOperand(Mode0Idx).getImm() && 138 (LatrCFAlu.getOperand(KBank0Idx).getImm() != 139 RootCFAlu.getOperand(KBank0Idx).getImm() || 140 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != 141 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { 152 if (LatrCFAlu.getOperand(Mode1Id [all...] |
H A D | AMDGPUGlobalISelUtils.cpp | 24 const MachineOperand &Op = Def->getOperand(1); 36 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset))) 37 return std::make_tuple(Def->getOperand(1).getReg(), Offset, Def); 40 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset)))) 41 return std::make_tuple(Def->getOperand(1).getReg(), Offset, Def);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVMergeBaseOffset.cpp | 83 HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI || 84 HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress || 85 HiLUI.getOperand(1).getOffset() != 0 || 86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) 88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg(); 91 LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO || 92 LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress || 93 LoADDI->getOperand(2).getOffset() != 0 || 94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) 106 HiLUI.getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXFMAMutate.cpp | 112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); 130 Register AddendSrcReg = AddendMI->getOperand(1).getReg(); 132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != 138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) 164 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { 186 Register OldFMAReg = MI.getOperand(0).getReg(); 190 Register Reg2 = MI.getOperand(2).getReg(); 191 Register Reg3 = MI.getOperand(3).getReg(); 218 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg(); 219 Register OtherProdReg = MI.getOperand(OtherProdO [all...] |
H A D | PPCMIPeephole.cpp | 167 return MI->getOperand(3).getImm(); 170 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) 171 return MI->getOperand(3).getImm(); 176 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) 177 return 32 + MI->getOperand(3).getImm(); 180 uint16_t Imm = MI->getOperand(2).getImm(); 334 int Immed = MI.getOperand(3).getImm(); 346 TRI->lookThruCopyLike(MI.getOperand( [all...] |
H A D | PPCPreEmitPeephole.cpp | 89 if (!BBI->getOperand(1).isImm()) 91 assert(BBI->getOperand(0).isReg() && 96 Register Reg = BBI->getOperand(0).getReg(); 97 int64_t Imm = BBI->getOperand(1).getImm(); 99 if (BBI->getOperand(0).isDead()) { 100 DeadOrKillToUnset = &BBI->getOperand(0); 114 DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx); 126 assert(AfterBBI->getOperand(0).isReg() && 130 if (!AfterBBI->getOperand(1).isImm() || 131 AfterBBI->getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZAsmPrinter.cpp | 36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 37 .addImm(MI->getOperand(1).getImm()); 40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) 42 .addImm(MI->getOperand(2).getImm()); 50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 51 .addImm(MI->getOperand(1).getImm()); 54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) 56 .addImm(MI->getOperand( [all...] |
H A D | SystemZShortenInst.cpp | 68 !MI.getOperand(0).isTied()) 77 Register Reg = MI.getOperand(0).getReg(); 92 uint64_t Imm = MI.getOperand(1).getImm(); 95 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); 100 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); 101 MI.getOperand(1).setImm(Imm >> 16); 109 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) { 119 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && 120 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { 131 if (SystemZMC::getFirstReg(MI.getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) 98 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) 128 OutOps.push_back(Op.getOperand(0)); 163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 164 N->getOperand(2) }; 170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 171 N->getOperand(2) }; 177 SDValue Ops[] = { N->getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCompound.cpp | 96 DstReg = MI.getOperand(0).getReg(); 97 Src1Reg = MI.getOperand(1).getReg(); 98 Src2Reg = MI.getOperand(2).getReg(); 110 DstReg = MI.getOperand(0).getReg(); 111 SrcReg = MI.getOperand(1).getReg(); 122 DstReg = MI.getOperand(0).getReg(); 123 SrcReg = MI.getOperand(1).getReg(); 132 DstReg = MI.getOperand(0).getReg(); 141 DstReg = MI.getOperand(0).getReg(); 142 Src1Reg = MI.getOperand( [all...] |
H A D | HexagonMCDuplexInfo.cpp | 202 DstReg = MCI.getOperand(0).getReg(); 203 SrcReg = MCI.getOperand(1).getReg(); 220 DstReg = MCI.getOperand(0).getReg(); 221 SrcReg = MCI.getOperand(1).getReg(); 241 DstReg = MCI.getOperand(0).getReg(); 242 SrcReg = MCI.getOperand(1).getReg(); 251 DstReg = MCI.getOperand(0).getReg(); 252 SrcReg = MCI.getOperand(1).getReg(); 261 DstReg = MCI.getOperand(0).getReg(); 262 SrcReg = MCI.getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiInstPrinter.cpp | 49 unsigned AluCode = MI->getOperand(3).getImm(); 51 (MI->getOperand(2).getImm() == AddOffset || 52 MI->getOperand(2).getImm() == -AddOffset); 56 unsigned AluCode = MI->getOperand(3).getImm(); 61 unsigned AluCode = MI->getOperand(3).getImm(); 66 if (MI->getOperand(2).getImm() < 0) 77 << getRegisterName(MI->getOperand(1).getReg()) << "], %" 78 << getRegisterName(MI->getOperand(0).getReg()); 83 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) 84 << "], %" << getRegisterName(MI->getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 100 const MCOperand &Dst = MI->getOperand(0); 101 const MCOperand &MO1 = MI->getOperand(1); 102 const MCOperand &MO2 = MI->getOperand(2); 103 const MCOperand &MO3 = MI->getOperand(3); 123 const MCOperand &Dst = MI->getOperand(0); 124 const MCOperand &MO1 = MI->getOperand(1); 125 const MCOperand &MO2 = MI->getOperand(2); 150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 164 if (MI->getOperand(2).getReg() == ARM::SP && 165 MI->getOperand( [all...] |
H A D | ARMMCTargetDesc.cpp | 40 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && 41 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && 44 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { 45 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { 46 if (MI.getOperand(4).isImm() && MI.getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZInstPrinter.cpp | 71 int64_t Value = MI->getOperand(OpNum).getImm(); 78 int64_t Value = MI->getOperand(OpNum).getImm(); 150 const MCOperand &MO = MI->getOperand(OpNum); 165 const MCOperand &MO = MI->getOperand(OpNum + 1); 183 printOperand(MI->getOperand(OpNum), &MAI, O); 188 printAddress(MI->getOperand(OpNum).getReg(), 189 MI->getOperand(OpNum + 1).getImm(), 0, O); 194 printAddress(MI->getOperand(OpNum).getReg(), 195 MI->getOperand(OpNum + 1).getImm(), 196 MI->getOperand(OpNu [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsInstructionSelector.cpp | 101 Register DstReg = I.getOperand(0).getReg(); 178 const Register ValueReg = I.getOperand(0).getReg(); 265 isRegInGprb(I.getOperand(0).getReg(), MRI)) { 267 .add(I.getOperand(0)) 268 .add(I.getOperand(1)) 269 .add(I.getOperand(2)); 272 Mul->getOperand(3).setIsDead(true); 273 Mul->getOperand(4).setIsDead(true); 292 .add(I.getOperand(1)) 293 .add(I.getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyDebugValueManager.cpp | 34 DBI->getOperand(0).setReg(Reg); 43 Clone->getOperand(0).setReg(NewReg); 50 MachineOperand &Op = DBI->getOperand(0);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFeatures.h | 78 return Instr->getOperand(2).getReg() != ARM::PC; 83 return Instr->getOperand(0).getReg() != ARM::PC; 85 return Instr->getOperand(0).getReg() != ARM::PC && 86 Instr->getOperand(2).getReg() != ARM::PC; 89 return Instr->getOperand(0).getReg() != ARM::PC && 90 Instr->getOperand(1).getReg() != ARM::PC;
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFRegisterInfo.cpp | 75 while (!MI.getOperand(i).isFI()) { 81 int FrameIndex = MI.getOperand(i).getIndex(); 88 MI.getOperand(i).ChangeToRegister(FrameReg, false); 89 Register reg = MI.getOperand(i - 1).getReg(); 97 MI.getOperand(i + 1).getImm(); 108 Register reg = MI.getOperand(i - 1).getReg(); 119 MI.getOperand(i).ChangeToRegister(FrameReg, false); 120 MI.getOperand(i + 1).ChangeToImmediate(Offset);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 137 MachineOperand &Dst = MI.getOperand(0); 138 MachineOperand &Src = MI.getOperand(1); 155 MachineOperand &Dst = MI.getOperand(0); 156 MachineOperand &Src1 = MI.getOperand(1); 157 MachineOperand &Src2 = MI.getOperand(2); 172 MachineOperand &Dst = MI.getOperand(0); 173 MachineOperand &Src1 = MI.getOperand(1); 174 MachineOperand &Src2 = MI.getOperand(2); 186 MachineOperand &Dst = MI.getOperand(0); 187 MachineOperand &Src = MI.getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 62 assert(Inst.getOperand(2).isImm()); 64 int64_t Shift = Inst.getOperand(2).getImm(); 70 Inst.getOperand(2).setImm(Shift); 95 unsigned RegOp0 = Inst.getOperand(0).getReg(); 96 unsigned RegOp1 = Inst.getOperand(1).getReg(); 116 Inst.getOperand(0).setReg(RegOp1); 117 Inst.getOperand(1).setReg(RegOp0); 239 const MCOperand &MO = MI.getOperand(OpNo); 261 const MCOperand &MO = MI.getOperand(OpNo); 283 const MCOperand &MO = MI.getOperand(OpN [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRExpandPseudoInsts.cpp | 145 Register DstReg = MI.getOperand(0).getReg(); 146 Register SrcReg = MI.getOperand(2).getReg(); 147 bool DstIsDead = MI.getOperand(0).isDead(); 148 bool DstIsKill = MI.getOperand(1).isKill(); 149 bool SrcIsKill = MI.getOperand(2).isKill(); 150 bool ImpIsDead = MI.getOperand(3).isDead(); 165 MIBHI->getOperand(3).setIsDead(); 168 MIBHI->getOperand(4).setIsKill(); 178 Register DstReg = MI.getOperand(0).getReg(); 179 Register SrcReg = MI.getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/ |
H A D | ProfileSummary.cpp | 89 MDString *KeyMD = dyn_cast<MDString>(MD->getOperand(0)); 90 ConstantAsMetadata *ValMD = dyn_cast<ConstantAsMetadata>(MD->getOperand(1)); 103 MDString *KeyMD = dyn_cast<MDString>(MD->getOperand(0)); 104 MDString *ValMD = dyn_cast<MDString>(MD->getOperand(1)); 116 MDString *KeyMD = dyn_cast<MDString>(MD->getOperand(0)); 119 MDTuple *EntriesMD = dyn_cast<MDTuple>(MD->getOperand(1)); 127 dyn_cast<ConstantAsMetadata>(EntryMD->getOperand(0)); 129 dyn_cast<ConstantAsMetadata>(EntryMD->getOperand(1)); 131 dyn_cast<ConstantAsMetadata>(EntryMD->getOperand(2)); 147 auto &FormatMD = Tuple->getOperand( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | GISelKnownBits.cpp | 45 int FrameIdx = MI.getOperand(1).getIndex(); 66 return getKnownBits(MI.getOperand(0).getReg()); 126 MachineOperand Dst = MI.getOperand(0); 127 MachineOperand Src = MI.getOperand(1); 158 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, 163 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, 170 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, 172 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, 184 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); 197 computeKnownBitsImpl(MI.getOperand( [all...] |