Searched refs:getMachineOpValue (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
172 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:SystemZMCCodeEmitter
186 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
187 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
196 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
197 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
206 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
207 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
208 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
217 uint64_t Base = getMachineOpValue(M
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp47 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
59 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
72 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
85 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
97 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
111 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
115 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
129 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
133 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
147 unsigned RegBits = getMachineOpValue(M
261 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:PPCMCCodeEmitter
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H A DPPCMCCodeEmitter.h81 /// getMachineOpValue - Return binary encoding of operand. If the machine
83 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp66 /// getMachineOpValue - Return binary encoding of operand. If the machine
68 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
115 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
124 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:SparcMCCodeEmitter
155 return getMachineOpValue(MI, MO, Fixups, STI);
190 return getMachineOpValue(MI, MO, Fixups, STI);
203 return getMachineOpValue(MI, MO, Fixups, STI);
216 return getMachineOpValue(MI, MO, Fixups, STI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp539 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
744 /// getMachineOpValue - Return binary encoding of operand. If the machine
747 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:MipsMCCodeEmitter
773 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
775 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
789 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
791 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
803 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
805 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
817 unsigned RegBits = getMachineOpValue(M
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H A DMipsMCCodeEmitter.h178 // getMachineOpValue - Return binary encoding of operand. If the machin
180 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.h42 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:llvm::AMDGPUMCCodeEmitter
H A DSIMCCodeEmitter.cpp64 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
304 OS.write((uint8_t)getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i),
359 return getMachineOpValue(MI, MO, Fixups, STI);
451 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:SIMCCodeEmitter
H A DR600MCCodeEmitter.cpp53 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
171 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:R600MCCodeEmitter
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp55 // getMachineOpValue - Return binary encoding of operand. If the machine
57 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
107 // getMachineOpValue - Return binary encoding of operand. If the machine
109 unsigned LanaiMCCodeEmitter::getMachineOpValue( function in class:llvm::LanaiMCCodeEmitter
212 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
283 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
293 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp51 // getMachineOpValue - Return binary encoding of operand. If the machin
53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
86 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:BPFMCCodeEmitter
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.h68 unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
73 // helper routine for getMachineOpValue()
H A DHexagonMCCodeEmitter.cpp719 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h94 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
H A DAVRMCCodeEmitter.cpp250 unsigned AVRMCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:llvm::AVRMCCodeEmitter
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
101 unsigned MSP430MCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:llvm::MSP430MCCodeEmitter
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp72 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
216 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:RISCVMCCodeEmitter
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp60 /// getMachineOpValue - Return binary encoding of operand. If the machine
62 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
198 /// getMachineOpValue - Return binary encoding of operand. If the machine
201 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:AArch64MCCodeEmitter
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp84 /// getMachineOpValue - Return binary encoding of operand. If the machine
86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
557 /// getMachineOpValue - Return binary encoding of operand. If the machine
560 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:ARMMCCodeEmitter

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