/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.cpp | 166 assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type"); 168 Res.addDefToMIB(*getMRI(), MIB); 176 assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type"); 178 Res.addDefToMIB(*getMRI(), MIB); 185 assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type"); 186 assert(Res.getLLTTy(*getMRI()).getAddressSpace() == 191 Res.addDefToMIB(*getMRI(), MIB); 217 assert(Res.getLLTTy(*getMRI()).isPointer() && 218 Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) [all...] |
H A D | CSEMIRBuilder.cpp | 65 B.addNodeIDRegType(Op.getLLTTy(*getMRI())); 161 SrcOps[1].getReg(), *getMRI())) 172 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI())) 190 GISelInstProfileBuilder ProfBuilder(ID, *getMRI()); 211 LLT Ty = Res.getLLTTy(*getMRI()); 216 GISelInstProfileBuilder ProfBuilder(ID, *getMRI()); 238 LLT Ty = Res.getLLTTy(*getMRI()); 243 GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
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H A D | CallLowering.cpp | 135 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 237 MIRBuilder.getMRI()->createGenericVirtualRegister(NewLLT); 328 MIRBuilder.getMRI()->createGenericVirtualRegister(VATy);
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H A D | RegisterBankInfo.cpp | 441 MachineRegisterInfo &MRI = OpdMapper.getMRI();
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H A D | CombinerHelper.cpp | 936 MachineRegisterInfo &MRI = *MIB.getMRI();
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H A D | LegalizerHelper.cpp | 4433 const LLT Ty = Dst.getLLTTy(*B.getMRI());
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | ConstantFoldingMIRBuilder.h | 53 ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI())) 64 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
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H A D | RegisterBankInfo.h | 334 MachineRegisterInfo &getMRI() const { return MRI; } function in class:llvm::RegisterBankInfo::OperandsMapper
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H A D | MachineIRBuilder.h | 271 MachineRegisterInfo *getMRI() { return State.MRI; } function in class:llvm::MachineIRBuilder 272 const MachineRegisterInfo *getMRI() const { return State.MRI; } function in class:llvm::MachineIRBuilder 1342 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIPeepholeSDWA.cpp | 128 MachineRegisterInfo *getMRI() const { function in class:__anon2129::SDWAOperand 358 MachineOperand *PotentialMO = findSingleRegUse(getReplacedOperand(), getMRI()); 442 MachineRegisterInfo *MRI = getMRI(); 496 getMRI()->clearKillFlags(MO.getReg());
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H A D | SIMachineScheduler.h | 458 MachineRegisterInfo *getMRI() { return &MRI; } function in class:llvm::final
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H A D | SIMachineScheduler.cpp | 330 MachineRegisterInfo *MRI = DAG->getMRI(); 1749 PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg); 1759 PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg);
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H A D | AMDGPURegisterBankInfo.cpp | 681 MachineRegisterInfo *MRI = B.getMRI(); 1242 B.getMRI()->setRegBank(Cmp.getReg(0), AMDGPU::SGPRRegBank); 1304 std::tie(BaseReg, ImmOffset) = getBaseWithConstantOffset(*B.getMRI(), 1360 MachineRegisterInfo &MRI = *B.getMRI(); 1437 MachineRegisterInfo &MRI = *B.getMRI(); 1472 MachineRegisterInfo &MRI = OpdMapper.getMRI();
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H A D | AMDGPUCallLowering.cpp | 519 MachineRegisterInfo &MRI = *B.getMRI();
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H A D | AMDGPULegalizerInfo.cpp | 1656 B.getMRI()->createGenericVirtualRegister(ConstPtrTy); 1667 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); 1848 MachineRegisterInfo &MRI = *B.getMRI();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsRegisterBankInfo.cpp | 669 MachineRegisterInfo &MRI = OpdMapper.getMRI();
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H A D | MipsInstructionSelector.cpp | 162 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
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H A D | MipsCallLowering.cpp | 109 MIRBuilder.getMRI()->addLiveIn(PhysReg);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallLowering.cpp | 409 MIRBuilder.getMRI()->addLiveIn(PhysReg);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallLowering.cpp | 307 MIRBuilder.getMRI()->addLiveIn(PhysReg);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstructionSelector.cpp | 2903 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 3476 MachineRegisterInfo &MRI = *MIB.getMRI(); 3576 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 3678 MachineRegisterInfo &MRI = *MIB.getMRI(); 3870 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 4772 MachineRegisterInfo &MRI = *MIB.getMRI();
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H A D | AArch64CallLowering.cpp | 113 MIRBuilder.getMRI()->addLiveIn(PhysReg);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 1205 const MCRegisterInfo *getMRI() const { function in class:__anon2091::AMDGPUAsmParser 1638 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); 2957 unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); 2998 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;
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