Searched refs:WR4HW (Results 1 - 2 of 2) sorted by relevance

/freebsd-11-stable/sys/arm/at91/
H A Dat91_smc.c36 * RD4HW()/WR4HW() read and write at91 hardware register space directly. They
51 WR4HW(uint32_t devbase, uint32_t regoff, uint32_t val) function
64 WR4HW(base, SMC_SETUP, SMC_SETUP_NCS_RD_SETUP(smc->ncs_rd_setup) |
68 WR4HW(base, SMC_PULSE, SMC_PULSE_NCS_RD_PULSE(smc->ncs_rd_pulse) |
72 WR4HW(base, SMC_CYCLE, SMC_CYCLE_NRD_CYCLE(smc->nrd_cycle) |
74 WR4HW(base, SMC_MODE, smc->mode | SMC_MODE_TDF_CYCLES(smc->tdf_cycles));
81 WR4HW(AT91SAM9260_MATRIX_BASE, AT91SAM9260_EBICSA, (1 << bank) |
89 WR4HW(AT91SAM9260_MATRIX_BASE, AT91SAM9260_EBICSA, ~(1 << bank) &
H A Dboard_tsc4370.c55 * RD4HW()/WR4HW() read and write at91rm9200 hardware register space directly.
68 WR4HW(uint32_t devbase, uint32_t regoff, uint32_t val) function
110 WR4HW(AT91RM92_PMC_BASE, PMC_MCKR, mckr);
179 WR4HW(AT91RM92_DBGU_BASE, USART_BRGR, BAUD2DIVISOR(115200));
205 WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_TWI);
211 WR4HW(AT91RM92_TWI_BASE, TWI_IDR, 0xffffffff);
212 WR4HW(AT91RM92_TWI_BASE, TWI_CR, TWI_CR_SWRST);
213 WR4HW(AT91RM92_TWI_BASE, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
214 WR4HW(AT91RM92_TWI_BASE, TWI_CWGR, twiCkDiv | twiChDiv | twiClDiv);
229 WR4HW(AT91RM92_TWI_BAS
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