Searched refs:VALU (Results 1 - 4 of 4) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h81 int checkVALUHazards(MachineInstr *VALU);
H A DSIDefines.h22 VALU = 1 << 1,
31 // VALU instruction formats.
H A DSIInstrInfo.h342 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
346 return get(Opcode).TSFlags & SIInstrFlags::VALU;
771 /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
894 /// Replace this instruction's opcode with the equivalent VALU
896 /// VALU if necessary. If present, \p MDT is updated.
H A DGCNHazardRecognizer.cpp547 // SGPR was written by a VALU instruction.
588 // SGPR was written by a VALU Instruction.
607 // Check for DPP VGPR read after VALU VGPR write and EXEC write.
634 // v_div_fmas requires 4 wait states after a write to vcc from a VALU
742 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { argument
751 for (const MachineOperand &Def : VALU->defs()) {

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