Searched refs:UnitSize (Results 1 - 7 of 7) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/fuzzer/ |
H A D | FuzzerLoop.cpp | 181 size_t UnitSize = CurrentUnitSize; local 182 if (UnitSize <= kMaxUnitSizeToPrint) { 183 PrintHexArray(CurrentUnitData, UnitSize, "\n"); 184 PrintASCII(CurrentUnitData, UnitSize, "\n"); 186 WriteUnitToFileWithPrefix({CurrentUnitData, CurrentUnitData + UnitSize},
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/ObjectYAML/ |
H A D | DWARFYAML.cpp | 92 IO.mapRequired("UnitSize", Section.UnitSize);
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H A D | DWARFEmitter.cpp | 123 writeInteger((uint32_t)Sect.UnitSize, OS, IsLittleEndian);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/ObjectYAML/ |
H A D | DWARFYAML.h | 84 uint32_t UnitSize; member in struct:llvm::DWARFYAML::PubSection
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 538 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 543 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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H A D | PPCISelLowering.cpp | 1640 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, argument 1644 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 1647 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 1648 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 1649 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 1650 LHSStart+j+i*UnitSize) || 1651 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize 1664 isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) argument 1689 isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 10171 unsigned UnitSize = 0; local 10180 UnitSize = 1; 10182 UnitSize = 2; 10188 UnitSize = 16; 10190 UnitSize = 8; 10193 if (UnitSize == 0) 10194 UnitSize = 4; 10198 bool IsNeon = UnitSize >= 8; 10201 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass 10202 : UnitSize [all...] |
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