Searched refs:SubReg1 (Results 1 - 8 of 8) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp207 unsigned SubReg1; local
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
299 unsigned Src1 = 0, SubReg1; local
324 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
348 SubReg1 = 0;
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
H A DAArch64ISelLowering.cpp12849 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32); local
12850 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
12897 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; local
12899 std::swap(SubReg1, SubReg2);
12900 Results.push_back(DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegBankReassign.cpp542 unsigned SubReg1 = OperandMasks[I].SubReg;
549 LLVM_DEBUG(dbgs() << "Conflicting operands: " << printReg(Reg1, SubReg1) <<
557 unsigned FreeBanks1 = getFreeBanks(Reg1, SubReg1, Mask1, UsedBanks);
H A DAMDGPUISelDAGToDAG.cpp809 SDValue RC, SubReg0, SubReg1; local
814 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
818 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
823 N->getOperand(1), SubReg1 };
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp178 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); local
205 SubReg0 = SubReg1;
223 CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1781 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); local
1782 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1792 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); local
1793 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1803 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); local
1804 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1814 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); local
1815 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1826 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); local
1829 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1841 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); local
1856 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); local
[all...]
H A DARMISelLowering.cpp9211 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); local
9212 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp398 unsigned SubReg1 = MI.getOperand(1).getSubReg(); local
409 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
441 MI.getOperand(2).setSubReg(SubReg1);

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