Searched refs:SrcRB (Results 1 - 4 of 4) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 575 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); local
577 DstRB = SrcRB;
578 else if (!SrcRB)
579 SrcRB = DstRB;
582 assert(DstRB && SrcRB && "Both RegBank were nullptr");
585 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size),
586 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
601 const RegisterBank &SrcRB = local
604 DefaultMappingID, copyCost(DstRB, SrcRB, Size),
605 getCopyMapping(DstRB.getID(), SrcRB
[all...] |
| H A D | AArch64InstructionSelector.cpp | 1691 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); local
1694 assert(SrcRB.getID() == AArch64::FPRRegBankID &&
1697 (void)SrcRB;
2046 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); local
2048 if (DstRB.getID() != SrcRB.getID()) {
2061 getRegClassForTypeOnBank(SrcTy, SrcRB, RBI);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 719 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); local
721 if (DstRB.getID() != SrcRB.getID()) {
728 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
808 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); local
810 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
894 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); local
896 assert(DstRB.getID() == SrcRB.getID() &&
903 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1255 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
1260 DstRB = SrcRB;
1263 if (SrcRB != DstRB)
1271 = TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB, *MRI);
1644 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
1655 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB,
1705 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
1713 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(SrcTy, *SrcRB,
1728 if (SrcRB->getID() == AMDGPU::SGPRRegBankID) {
1743 if (SrcRB
[all...] |
Completed in 86 milliseconds