Searched refs:SlotIdx (Results 1 - 5 of 5) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterPressure.cpp581 SlotIndex SlotIdx = LIS.getInstructionIndex(MI);
586 LiveQueryResult LRQ = LR->Query(SlotIdx);
797 SlotIndex SlotIdx;
799 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
833 LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx);
863 SlotIndex SlotIdx;
865 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
869 static_cast<IntervalPressure&>(P).openTop(SlotIdx);
885 SlotIndex SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
886 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
[all...]
H A DScheduleDAGInstrs.cpp820 SlotIndex SlotIdx = LIS->getInstructionIndex(MI); local
821 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
H A DMachineScheduler.cpp1408 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); local
1409 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
1442 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); local
1443 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp426 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); local
427 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
H A DGCNIterativeScheduler.cpp399 auto SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); local
400 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);

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