Searched refs:Shr (Results 1 - 13 of 13) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/clang/include/clang/AST/ |
| H A D | StmtVisitor.h | 129 BINOP_FALLBACK(Shr)
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| H A D | RecursiveASTVisitor.h | 64 OPERATOR(Rem) OPERATOR(Add) OPERATOR(Sub) OPERATOR(Shl) OPERATOR(Shr) \
72 OPERATOR(Shl) OPERATOR(Shr) OPERATOR(And) OPERATOR(Or) OPERATOR(Xor)
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 500 if (Instruction *Shr = dyn_cast<Instruction>(I->getOperand(0)))
501 if (Value *R = simplifyShrShlDemandedBits(Shr, *ShrAmt, I, *SA,
934 InstCombiner::simplifyShrShlDemandedBits(Instruction *Shr, const APInt &ShrOp1, argument
941 Value *VarX = Shr->getOperand(0);
957 bool isLshr = (Shr->getOpcode() == Instruction::LShr);
973 if (!Shr->hasOneUse())
987 if (cast<BinaryOperator>(Shr)->isExact())
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| H A D | InstCombineInternal.h | 855 Instruction *Shr, const APInt &ShrOp1, Instruction *Shl,
946 Instruction *foldICmpShrConstant(ICmpInst &Cmp, BinaryOperator *Shr,
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| H A D | InstCombineCompares.cpp | 2164 BinaryOperator *Shr,
2168 Value *X = Shr->getOperand(0);
2170 if (Cmp.isEquality() && Shr->isExact() && Shr->hasOneUse() &&
2175 if (Cmp.isEquality() && match(Shr->getOperand(0), m_APInt(ShiftVal)))
2176 return foldICmpShrConstConst(Cmp, Shr->getOperand(1), C, *ShiftVal);
2179 if (!match(Shr->getOperand(1), m_APInt(ShiftAmt)))
2189 bool IsAShr = Shr->getOpcode() == Instruction::AShr;
2190 bool IsExact = Shr->isExact();
2191 Type *ShrTy = Shr
2163 foldICmpShrConstant(ICmpInst &Cmp, BinaryOperator *Shr, const APInt &C) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyIndVar.cpp | 761 /// Annotate the Shr in (X << IVOperand) >> C as exact using the
777 BinaryOperator *Shr = cast<BinaryOperator>(U); local
778 if (!Shr->isExact() && IVRange.getUnsignedMin().uge(*C)) {
779 Shr->setIsExact(true);
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/AST/Interp/ |
| H A D | Interp.h | 842 // Shr, Shl
896 inline bool Shr(InterpState &S, CodePtr OpPC) {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 1461 auto Shr = B.buildAShr(S64, FractMask, Exp);
1462 auto Not = B.buildNot(S64, Shr);
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| H A D | AMDGPUISelLowering.cpp | 2110 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); local
2111 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 4309 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4310 MIRBuilder.buildTrunc(Dst, Shr);
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 796 HANDLEBINOP(Shr)
4613 COMPOUND_OP(Shr);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 6236 SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Src, ShiftConst);
6239 SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
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| H A D | DAGCombiner.cpp | 20419 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); local
20421 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
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