Searched refs:Shifted (Results 1 - 8 of 8) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/clang/lib/Tooling/ASTDiff/
H A DASTDiff.cpp149 int findPositionInParent(NodeId Id, bool Shifted = false) const;
338 int SyntaxTree::Impl::findPositionInParent(NodeId Id, bool Shifted) const {
345 if (Shifted)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp2193 unsigned Shifted = 0; local
2200 Shifted += 2;
2209 if (Shifted > 24)
2210 Value = Value >> (Shifted - 24);
2212 Value = Value << (24 - Shifted);
/freebsd-11-stable/contrib/llvm-project/clang/lib/Format/
H A DFormat.cpp2366 auto Shifted = tooling::Replacement(FileName, NewOffset, 0,
2368 Result = Result.merge(tooling::Replacements(Shifted));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DScalarEvolution.cpp5148 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this);
5149 const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false);
5150 if (Shifted != getCouldNotCompute() &&
5158 ValueExprMap[SCEVCallbackVH(PN, this)] = Shifted;
5159 return Shifted;
10868 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(),
10870 if (const auto *ShiftedAddRec = dyn_cast<SCEVAddRecExpr>(Shifted))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1991 Register Shifted = MRI.createGenericVirtualRegister(Ty); local
1995 .addDef(Shifted)
1998 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp5520 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted"); local
5522 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit");
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12305 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, local
12307 auto Final = Shifted;
12311 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp552 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
6231 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
6232 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
6235 SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, argument
6246 EVT VT = Shifted.getValueType();
6249 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,

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