/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | DemandedBits.cpp | 162 uint64_t ShiftAmt = SA->urem(BitWidth); local 164 ShiftAmt = BitWidth - ShiftAmt; 167 AB = AOut.lshr(ShiftAmt); 169 AB = AOut.shl(BitWidth - ShiftAmt); 187 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); local 188 AB = AOut.lshr(ShiftAmt); 194 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); 196 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt); 204 uint64_t ShiftAmt local 218 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); local [all...] |
H A D | ValueTracking.cpp | 967 unsigned ShiftAmt = SA->getLimitedValue(BitWidth-1); local 970 Known.Zero = KZF(Known.Zero, ShiftAmt); 971 Known.One = KOF(Known.One, ShiftAmt); 1018 for (unsigned ShiftAmt = 0; ShiftAmt < BitWidth; ++ShiftAmt) { 1021 if ((ShiftAmt & ~ShiftAmtKZ) != ShiftAmt) 1023 if ((ShiftAmt | ShiftAmtKO) != ShiftAmt) 1610 uint64_t ShiftAmt = SA->urem(BitWidth); local [all...] |
H A D | ConstantFolding.cpp | 214 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); local 229 ConstantInt::get(Src->getType(), ShiftAmt)); 230 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize; 261 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); local 266 ConstantInt::get(Src->getType(), ShiftAmt)); 267 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandImm.cpp | 71 unsigned ShiftAmt = 0; local 74 for (; ShiftAmt < 64; ShiftAmt += 16) { 75 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; 83 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); 91 for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) { 92 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; 98 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); [all...] |
H A D | AArch64ConditionOptimizer.cpp | 174 unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm()); local 178 } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
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H A D | AArch64ISelDAGToDAG.cpp | 343 unsigned ShiftAmt; local 346 ShiftAmt = 0; 348 ShiftAmt = 12; 353 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); 2020 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); local 2021 Mask <<= ShiftAmt; local 2023 Mask.lshrInPlace(ShiftAmt); 2028 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); local 2029 Mask.lshrInPlace(ShiftAmt); 2031 Mask <<= ShiftAmt; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/ADT/ |
H A D | APInt.h | 205 void shlSlowCase(unsigned ShiftAmt); 208 void lshrSlowCase(unsigned ShiftAmt); 211 void ashrSlowCase(unsigned ShiftAmt); 920 /// \returns *this after shifting left by ShiftAmt 921 APInt &operator<<=(unsigned ShiftAmt) { argument 922 assert(ShiftAmt <= BitWidth && "Invalid shift amount"); 924 if (ShiftAmt == BitWidth) 927 U.VAL <<= ShiftAmt; 930 shlSlowCase(ShiftAmt); 938 /// \returns *this after shifting left by ShiftAmt 970 ashrInPlace(unsigned ShiftAmt) argument 994 lshrInPlace(unsigned ShiftAmt) argument 1050 R <<= ShiftAmt; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineSimplifyDemanded.cpp | 505 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); 506 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); 511 DemandedMaskIn.setHighBits(ShiftAmt+1); 513 DemandedMaskIn.setHighBits(ShiftAmt); 518 Known.Zero <<= ShiftAmt; 519 Known.One <<= ShiftAmt; 521 if (ShiftAmt) 522 Known.Zero.setLowBits(ShiftAmt); 529 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local 532 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); 568 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local 729 uint64_t ShiftAmt = SA->urem(BitWidth); local [all...] |
H A D | InstCombineCasts.cpp | 794 unsigned ShiftAmt = Cst->getZExtValue(); local 801 if (ShiftAmt <= MaxAmt) { 804 std::min(ShiftAmt, ASize - 1))); 806 Value *Shift = Builder.CreateAShr(A, std::min(ShiftAmt, ASize - 1)); 1038 uint64_t ShiftAmt = Amt->getZExtValue(); 1039 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0; 1273 unsigned ShiftAmt = KnownZeroMask.countTrailingZeros(); local 1275 if (ShiftAmt) 1277 ConstantInt::get(In->getType(), ShiftAmt)); 1287 unsigned ShiftAmt = KnownZeroMask.countLeadingZeros(); local [all...] |
H A D | InstCombineCompares.cpp | 2030 const APInt *ShiftAmt; local 2031 if (!match(Shl->getOperand(1), m_APInt(ShiftAmt))) 2037 if (ShiftAmt->uge(TypeBits)) 2049 // icmp Pred (shl nsw X, ShiftAmt), C --> icmp Pred X, (C >>s ShiftAmt) 2050 APInt ShiftedC = C.ashr(*ShiftAmt); 2054 C.ashr(*ShiftAmt).shl(*ShiftAmt) == C) { 2055 APInt ShiftedC = C.ashr(*ShiftAmt); 2064 APInt ShiftedC = (C - 1).ashr(*ShiftAmt) 2178 const APInt *ShiftAmt; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | VNCoercion.cpp | 118 uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy) - local 121 StoredVal, ConstantInt::get(StoredVal->getType(), ShiftAmt)); 368 unsigned ShiftAmt; local 370 ShiftAmt = Offset * 8; 372 ShiftAmt = (StoreSize - LoadSize - Offset) * 8; 373 if (ShiftAmt) 375 ConstantInt::get(SrcVal->getType(), ShiftAmt));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | AtomicExpandPass.cpp | 616 Value *ShiftAmt; member in struct:__anon1692::PartwordMaskValues 631 /// ShiftAmt: Number of bits to right-shift a WordSize value loaded 669 Ret.ShiftAmt = Builder.CreateShl(PtrLSB, 3); 672 Ret.ShiftAmt = 676 Ret.ShiftAmt = Builder.CreateTrunc(Ret.ShiftAmt, Ret.WordType, "ShiftAmt"); 678 ConstantInt::get(Ret.WordType, (1 << (ValueSize * 8)) - 1), Ret.ShiftAmt, 723 Builder.CreateLShr(Loaded, PMV.ShiftAmt), PMV.ValueType); 726 Builder.CreateZExt(NewVal, PMV.WordType), PMV.ShiftAmt); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 1708 unsigned ShiftAmt = Shift.getConstantOperandVal(1); local 1709 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3) 1720 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT); 1735 AM.Scale = 1 << ShiftAmt; 1775 unsigned ShiftAmt = Shift.getConstantOperandVal(1); local 1792 unsigned ScaleDown = (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt; 1829 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8); 1872 unsigned ShiftAmt local 3476 SDValue ShiftAmt = X.getOperand(1); local 3710 SDValue ShiftAmt = OrigShiftAmt; local [all...] |
H A D | X86ISelLowering.cpp | 11928 int ShiftAmt = Shift * ScalarSizeInBits / (ByteShift ? 8 : 1); 11938 return (int)ShiftAmt; 11952 int ShiftAmt = MatchShift(Shift, Scale, Left); 11953 if (0 < ShiftAmt) 11954 return ShiftAmt; 11974 int ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(), 11978 if (ShiftAmt < 0) { 11979 ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(), 11984 if (ShiftAmt < 0) 11991 DAG.getTargetConstant(ShiftAmt, D [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 676 auto ShiftAmt = local 678 auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt); 1212 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); local 1213 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1321 auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I); local 1322 auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt); 1549 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); local 1550 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 1992 Register ShiftAmt = MRI.createGenericVirtualRegister(Ty); local 1993 MIRBuilder.buildConstant(ShiftAmt, T 2124 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); local 2184 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize); local 3259 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); local 4069 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); local 4075 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); local 4184 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.h | 212 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.cpp | 1800 auto ShiftAmt = B.buildConstant(S32, 31); local 1801 MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank); 1802 B.buildAShr(DefRegs[1], DefRegs[0], ShiftAmt); 1854 auto ShiftAmt = B.buildConstant(LLT::scalar(32), DstTy.getSizeInBits() - 1); local 1855 auto Shl = B.buildShl(DstTy, Ext, ShiftAmt); 1858 B.buildAShr(DstReg, Shl, ShiftAmt); 1860 B.buildLShr(DstReg, Shl, ShiftAmt); 1864 MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank); 1906 auto ShiftAmt = B.buildConstant(S32, 16); local 1907 MRI.setRegBank(ShiftAmt 1915 auto ShiftAmt = B.buildConstant(S32, 16); local [all...] |
H A D | R600ISelLowering.cpp | 1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, local 1201 MaskedValue, ShiftAmt); 1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); 1416 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, local 1420 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | SCCP.cpp | 1594 if (auto *ShiftAmt = Op1LV.getConstantInt()) 1595 if (ShiftAmt->getLimitedValue() >= 1596 ShiftAmt->getType()->getScalarSizeInBits()) 1611 if (auto *ShiftAmt = Op1LV.getConstantInt()) 1612 if (ShiftAmt->getLimitedValue() >= 1613 ShiftAmt->getType()->getScalarSizeInBits())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/ |
H A D | APInt.cpp | 991 void APInt::ashrSlowCase(unsigned ShiftAmt) { 993 if (!ShiftAmt) 1000 unsigned WordShift = ShiftAmt / APINT_BITS_PER_WORD; 1001 unsigned BitShift = ShiftAmt % APINT_BITS_PER_WORD; 1040 void APInt::lshrSlowCase(unsigned ShiftAmt) { 1041 tcShiftRight(U.pVal, getNumWords(), ShiftAmt); 1052 void APInt::shlSlowCase(unsigned ShiftAmt) { 1053 tcShiftLeft(U.pVal, getNumWords(), ShiftAmt); 2260 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); 2266 Tmp.lshrInPlace(ShiftAmt); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1834 unsigned ShiftAmt; local 1839 ShiftAmt = 24; 1842 ShiftAmt = 16; 1846 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); 1847 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
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H A D | MipsISelLowering.cpp | 1665 Register ShiftAmt = RegInfo.createVirtualRegister(RC); local 1788 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1793 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1798 .addReg(MaskUpper).addReg(ShiftAmt); 1800 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1814 .addReg(ShiftAmt) 1914 Register ShiftAmt = RegInfo.createVirtualRegister(RC); local 1975 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1980 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1985 .addReg(MaskUpper).addReg(ShiftAmt); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 1242 unsigned ShiftAmt = V.getConstantOperandVal(1); local 1246 for (unsigned i = ShiftAmt; i < NumBits; ++i) 1247 Bits[i] = LHSBits[i - ShiftAmt]; 1249 for (unsigned i = 0; i < ShiftAmt; ++i) 1257 unsigned ShiftAmt = V.getConstantOperandVal(1); local 1261 for (unsigned i = 0; i < NumBits - ShiftAmt; ++i) 1262 Bits[i] = LHSBits[i + ShiftAmt]; 1264 for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i) 4602 SDValue ShiftAmt = local 4609 N0, ShiftAmt); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 1615 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize * (Ratio - 1); 1621 Tmp <<= ShiftAmt; 1622 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize; 1631 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize * (Ratio - 1); 1636 Elt.IntVal.lshrInPlace(ShiftAmt); 1640 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 3450 uint64_t ShiftAmt = ShiftCnst->getZExtValue(); 3473 NumBits = countTrailingOnes(MaskVal) - ShiftAmt; 3480 NumBits = NumZeros + NumOnes - ShiftAmt; 3486 if (ShiftAmt < NumZeros) { 3493 Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32);
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