Searched refs:ShOpc (Results 1 - 7 of 7) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, argument 54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) 58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); 59 O << getShiftOpcStr(ShOpc); 61 if (ShOpc != ARM_AM::rrx) { 391 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); 392 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 393 if (ShOpc == ARM_AM::rrx)
|
H A D | ARMMCCodeEmitter.cpp | 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 247 switch (ShOpc) {
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 197 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); local 198 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
|
H A D | ARMISelDAGToDAG.cpp | 2866 SDValue ShOpc = local 2869 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
|
H A D | ARMISelLowering.cpp | 6144 unsigned ShOpc = N->getOpcode(); local 6160 if (ShOpc == ISD::SRL) { 6169 } else if (ShOpc == ISD::SRA)
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 6018 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; 6024 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0),
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | [all...] |
Completed in 478 milliseconds