/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); local 1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); 1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); 1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); 1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); 1307 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); local 1310 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); 1313 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 681 SDValue SetCC = N->getOperand(0); 683 if ((SetCC.getOpcode() != ISD::SETCC) || 684 !SetCC.getOperand(0).getValueType().isInteger()) 708 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 711 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 712 SetCC.getOperand(1), 713 ISD::getSetCCInverse(CC, SetCC.getValueType())); 715 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, Fals [all...] |
H A D | MipsSEISelLowering.cpp | 985 SDValue SetCC = N->getOperand(0); local 987 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) 991 SetCC.getOperand(0), SetCC.getOperand(1), 992 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 21899 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer"); 22018 SDValue SetCC = getSETCC(Cond, Overflow, DL, DAG); 22020 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC); 24009 SDValue SetCC; 24012 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG); 24014 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); 24018 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG); 24020 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, Set [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 840 /// Return true if this is a SetCC-equivalent operation with only one use. 2029 SDValue SetCC = Z.getOperand(0); 2030 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 2031 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) || 2032 SetCC.getOperand(0).getOpcode() != ISD::AND || 2033 !isOneConstant(SetCC.getOperand(0).getOperand(1))) 2042 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT); 7075 llvm_unreachable("Unhandled SetCC Equivalent!"); 9232 // Extend SetCC uses if necessary. 9234 for (SDNode *SetCC 9578 SDValue SetCC = N->getOperand(0); local 9806 SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC); local [all...] |
H A D | LegalizeIntegerTypes.cpp | 939 SDValue SetCC; local 944 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers); 947 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1)); 949 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), 953 return DAG.getSExtOrTrunc(SetCC, dl, NVT); 1442 // Promote all the way up to the canonical SetCC type. 1535 // Promote all the way up to the canonical SetCC type.
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H A D | TargetLowering.cpp | 2844 /// either operand of the SetCC node is a bitwise-and instruction. 5461 // To produce final result we need to blend 2 vectors: 'SetCC' and 7421 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); 7422 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); 7443 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); 7444 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); 7599 // Truncate the result if SetCC returns a larger type than needed.
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 3631 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); local 3633 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); 3635 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); 3697 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); local 3699 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); 3701 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 4232 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, local 4235 return SetCC; 4236 return DAG.getZExtOrTrunc(SetCC, DL, VT); 4264 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, local 4267 return SetCC; 4268 return DAG.getZExtOrTrunc(SetCC, SL, VT); 4463 SDNode *SetCC = nullptr; local 4467 SetCC = Intr; 4468 Intr = SetCC->getOperand(0).getNode(); 4492 assert(!SetCC || [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 10546 /// Helper structure to keep track of SetCC information. 10552 /// Helper structure to be able to read SetCC information. If set to 12203 SDValue SetCC = local 12207 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, 12264 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); local 12268 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask);
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