Searched refs:RD1 (Results 1 - 9 of 9) sorted by relevance

/freebsd-11-stable/sys/arm/freescale/imx/
H A Dimx6_hdmi.c80 RD1(struct imx_hdmi_softc *sc, bus_size_t off) function
98 val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) &
105 val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) &
207 reg = RD1(sc, HDMI_PHY_CONF0);
218 reg = RD1(sc, HDMI_PHY_CONF0);
229 reg = RD1(sc, HDMI_PHY_CONF0);
240 reg = RD1(sc, HDMI_PHY_CONF0);
251 reg = RD1(sc, HDMI_PHY_CONF0);
262 reg = RD1(sc, HDMI_PHY_CONF0);
273 val = RD1(s
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/freebsd-11-stable/sys/dev/tpm/
H A Dtpm20.h142 RD1(struct tpm_sc *sc, bus_size_t off) function
183 WR1(sc, off, RD1(sc, off) | val);
H A Dtpm_tis.c308 *buf++ = RD1(sc, TPM_DATA_FIFO);
353 return ((RD1(sc, TPM_ACCESS) & mask) == mask);
356 if ((RD1(sc, TPM_ACCESS) & mask) == mask)
/freebsd-11-stable/sys/arm/nvidia/
H A Das3722_gpio.c497 rv = RD1(sc, AS3722_GPIO_SIGNAL_OUT, &tmp);
499 rv = RD1(sc, AS3722_GPIO_SIGNAL_IN, &tmp);
522 rv = RD1(sc, AS3722_GPIO_SIGNAL_OUT, &tmp);
569 rv = RD1(sc, AS3722_GPIO0_CONTROL + i, &pin->pin_ctrl_reg);
H A Das3722.c199 rv = RD1(sc, AS3722_ASIC_ID1, &reg);
208 rv = RD1(sc, AS3722_ASIC_ID2, &sc->chip_rev);
H A Das3722_regulators.c394 rv = RD1(sc->base_sc, sc->def->volt_reg, sel);
423 rv = RD1(sc->base_sc, AS3722_FUSE7, &val);
H A Das3722.h285 #define RD1(sc, reg, val) as3722_read(sc, reg, val) macro
/freebsd-11-stable/sys/dev/sdhci/
H A Dsdhci.c72 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) macro
192 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
194 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
196 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
198 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
206 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
251 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
262 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
452 if (RD1(slo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3137 Register RD1 = RegInfo.createVirtualRegister(RC); local
3138 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3150 .addReg(RD1)

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