Searched refs:RADEON_WRITE (Results 1 - 7 of 7) sorted by relevance

/freebsd-11-stable/sys/dev/drm/
H A Dr600_cp.c206 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
207 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
208 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
225 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
226 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
227 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
234 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
235 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
237 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
238 RADEON_WRITE(R600_MCD_WR_B_CNT
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H A Dradeon_irq.c51 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
64 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
152 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
155 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
165 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
231 RADEON_WRITE(RADEON_AIC_CNTL, tmp);
232 RADEON_WRITE(RADEON_AIC_CNTL,
240 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
241 RADEON_WRITE(RADEON_BUS_CNTL, tmp |
247 RADEON_WRITE(RADEON_MSI_REARM_E
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H A Dradeon_cp.c123 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
125 RADEON_WRITE(R520_MC_IND_INDEX, 0);
132 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
134 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
141 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
143 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
150 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
190 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
192 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
203 RADEON_WRITE(RADEON_MC_FB_LOCATIO
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H A Dradeon_drv.h1826 #define RADEON_WRITE(reg, val) \ macro
1842 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1849 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1854 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1855 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1856 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1861 RADEON_WRITE(RS480_NB_MC_INDEX, \
1863 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1864 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1869 RADEON_WRITE(RS690_MC_INDE
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H A Dradeon_state.c1930 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1932 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1934 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_irq.c50 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
63 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
151 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
153 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
162 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
264 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
265 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
300 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
302 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
H A Dradeon_drv.h1851 #define RADEON_WRITE(reg, val) \ macro
1867 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1874 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1879 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1880 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1881 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1886 RADEON_WRITE(RS480_NB_MC_INDEX, \
1888 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1889 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1894 RADEON_WRITE(RS690_MC_INDE
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