Searched refs:R0 (Results 1 - 25 of 82) sorted by relevance

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/freebsd-11-stable/sys/cddl/dev/dtrace/arm/
H A Dregset.h48 #define REG_PS R0
49 #define REG_R0 R0
/freebsd-11-stable/crypto/openssl/crypto/md4/
H A Dmd4_dgst.c114 R0(A, B, C, D, X(0), 3, 0);
117 R0(D, A, B, C, X(1), 7, 0);
120 R0(C, D, A, B, X(2), 11, 0);
123 R0(B, C, D, A, X(3), 19, 0);
126 R0(A, B, C, D, X(4), 3, 0);
129 R0(D, A, B, C, X(5), 7, 0);
132 R0(C, D, A, B, X(6), 11, 0);
135 R0(B, C, D, A, X(7), 19, 0);
138 R0(A, B, C, D, X(8), 3, 0);
141 R0(
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H A Dmd4_locl.h103 #define R0(a,b,c,d,k,s,t) { \ macro
/freebsd-11-stable/crypto/openssl/crypto/md5/
H A Dmd5_dgst.c114 R0(A, B, C, D, X(0), 7, 0xd76aa478L);
117 R0(D, A, B, C, X(1), 12, 0xe8c7b756L);
120 R0(C, D, A, B, X(2), 17, 0x242070dbL);
123 R0(B, C, D, A, X(3), 22, 0xc1bdceeeL);
126 R0(A, B, C, D, X(4), 7, 0xf57c0fafL);
129 R0(D, A, B, C, X(5), 12, 0x4787c62aL);
132 R0(C, D, A, B, X(6), 17, 0xa8304613L);
135 R0(B, C, D, A, X(7), 22, 0xfd469501L);
138 R0(A, B, C, D, X(8), 7, 0x698098d8L);
141 R0(
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H A Dmd5_locl.h115 #define R0(a,b,c,d,k,s,t) { \ macro
/freebsd-11-stable/contrib/ldns/
H A Dsha1.c37 /* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */
38 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30); macro
71 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
72 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(
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/freebsd-11-stable/crypto/openssh/openbsd-compat/
H A Dsha1.c40 * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
42 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30); macro
73 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
74 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(
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/freebsd-11-stable/crypto/openssl/crypto/md5/asm/
H A Dmd5-586.pl25 %Ltmp1=("R0",&Np($C), "R1",&Np($C), "R2",&Np($C), "R3",&Np($D));
27 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, # R0
43 sub R0 subroutine
52 &comment("R0 $ki");
61 &mov($tmp1,&Np($c)) if $pos < 1; # next tmp1 for R0
199 &comment("R0 section");
201 &R0(-2,$A,$B,$C,$D,$X, 0, 7,0xd76aa478);
202 &R0( 0,$D,$A,$B,$C,$X, 1,12,0xe8c7b756);
203 &R0( 0,$C,$D,$A,$B,$X, 2,17,0x242070db);
204 &R0(
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/freebsd-11-stable/contrib/wpa/src/crypto/
H A Dsha1-internal.c143 /* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */
144 #define R0(v,w,x,y,z,i) \ macro
198 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
199 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DSafeStackLayout.cpp112 StackRegion R0 = R; local
113 R.Start = R0.End = Start;
114 Regions.insert(&R, R0);
118 StackRegion R0 = R; local
119 R0.End = R.Start = End;
120 Regions.insert(&R, R0);
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_dlib_asm.S55 #define manta R0
69 #define mantl R0
156 #define manta R0
170 #define mantl R0
257 #define mantal R0
372 #define mantal R0
373 #define cff R0
379 #define c80 R0
381 #define ic R0
455 #define ia R0
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H A Dfastmath_dlib_asm.S57 #define manta R0
71 #define mantl R0
192 #define manta R0
206 #define mantl R0
321 #define mantal R0
/freebsd-11-stable/contrib/gdb/gdb/
H A Ddpx2-nat.c40 R0, R1, R2, R3, R4, R5, R6, R7,
H A Drs6000-tdep.c822 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
913 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2173 #define R0 { 0, 0, 0, 0, 0 }
2193 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R
2171 #define R0 macro
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
67 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
69 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
119 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
156 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
H A DARMInstrInfo.cpp43 NopInst.addOperand(MCOperand::createReg(ARM::R0));
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
/freebsd-11-stable/contrib/ntp/lib/isc/
H A Dsha1.c105 * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
107 #define R0(v,w,x,y,z,i) \ macro
140 #define nR0(v,w,x,y,z,i) R0(*v,*w,*x,*y,*z,i)
228 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
229 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h42 case Lanai::R0:
/freebsd-11-stable/sys/arm/include/
H A Dcpu-v6.h277 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
278 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
279 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
280 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
281 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
282 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
283 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
284 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
285 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
286 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
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/freebsd-11-stable/contrib/gcc/config/rs6000/
H A Ddarwin-world.asm69 SAVE_WORLD takes R0 (the caller`s caller`s return address) and R11
70 (the stack frame size) as parameters. It returns VRsave in R0 if
77 USES: R0 R11 R12 */
126 /* Restore CR from R0. No More Branches! */
165 USES: R0 R10 R11 R12 and R7 R8
200 USES: R0 R11 R12 [R7/R8]
211 /* R0 := old CR */
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp57 Reserved.set(AVR::R0);
222 BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
232 .addReg(AVR::R0, RegState::Kill);
H A DAVRFrameLowering.cpp76 // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
88 .addReg(AVR::R0, RegState::Kill)
91 .addReg(AVR::R0, RegState::Define)
92 .addReg(AVR::R0, RegState::Kill)
93 .addReg(AVR::R0, RegState::Kill)
167 // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
170 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
173 .addReg(AVR::R0, RegState::Kill);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp79 Value *L0, *L1, *R0, *R1;
85 m_c_Or(m_Shl(m_Value(L0), m_Value(L1)), m_LShr(m_Value(R0), Sub)));
86 if (RotL.match(V) && L0 == R0 && L1 == R1) {
94 m_c_Or(m_LShr(m_Value(L0), m_Value(L1)), m_Shl(m_Value(R0), Sub)));
95 if (RotR.match(V) && L0 == R0 && L1 == R1) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelDAGToDAG.cpp132 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
145 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
288 // Materialize zero constants as copies from R0. This allows the coalescer
292 SDLoc(Node), Lanai::R0, MVT::i32);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp596 static bool IsMovepDestinationRegPair(unsigned R0, unsigned R1) { argument
598 if ((R0 == Mips::A0 && R1 == Mips::S5) ||
599 (R0 == Mips::A0 && R1 == Mips::S6) ||
600 (R0 == Mips::A0 && R1 == Mips::A1) ||
601 (R0 == Mips::A0 && R1 == Mips::A2) ||
602 (R0 == Mips::A0 && R1 == Mips::A3) ||
603 (R0 == Mips::A1 && R1 == Mips::A2) ||
604 (R0 == Mips::A1 && R1 == Mips::A3) ||
605 (R0 == Mips::A2 && R1 == Mips::A3))

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