Searched refs:QueuePtr (Results 1 - 7 of 7) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.cpp60 << " QueuePtr: " << FI.second.QueuePtr
122 return std::make_pair(QueuePtr ? &QueuePtr : nullptr,
H A DSIMachineFunctionInfo.cpp33 QueuePtr(false),
136 QueuePtr = true;
204 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
207 return ArgInfo.QueuePtr.getRegister();
455 Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
H A DSIMachineFunctionInfo.h189 Optional<SIArgument> QueuePtr; member in struct:llvm::yaml::SIArgumentInfo
213 YamlIO.mapOptional("queuePtr", AI.QueuePtr);
390 bool QueuePtr : 1;
600 return QueuePtr;
740 return ArgInfo.QueuePtr.getRegister();
H A DAMDGPUArgumentUsageInfo.h126 ArgDescriptor QueuePtr; member in struct:llvm::AMDGPUFunctionArgInfo
H A DAMDGPUTargetMachine.cpp1107 parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1108 MFI->ArgInfo.QueuePtr, 2, 0) ||
H A DAMDGPULegalizerInfo.cpp1221 Register QueuePtr = MRI.createGenericVirtualRegister(
1225 if (!loadInputValue(QueuePtr, B, &MFI->getArgInfo().QueuePtr))
1245 B.materializePtrAdd(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
H A DSIISelLowering.cpp1743 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo);
4636 SDValue QueuePtr = CreateLiveInRegister( local
4640 QueuePtr, SDValue());
4700 SDValue QueuePtr = CreateLiveInRegister( local
4707 SDValue Ptr = DAG.getObjectPtrOffset(DL, QueuePtr, StructOffset);
4713 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,

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