Searched refs:QueuePtr (Results 1 - 7 of 7) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUArgumentUsageInfo.cpp | 60 << " QueuePtr: " << FI.second.QueuePtr 122 return std::make_pair(QueuePtr ? &QueuePtr : nullptr,
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H A D | SIMachineFunctionInfo.cpp | 33 QueuePtr(false), 136 QueuePtr = true; 204 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( 207 return ArgInfo.QueuePtr.getRegister(); 455 Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
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H A D | SIMachineFunctionInfo.h | 189 Optional<SIArgument> QueuePtr; member in struct:llvm::yaml::SIArgumentInfo 213 YamlIO.mapOptional("queuePtr", AI.QueuePtr); 390 bool QueuePtr : 1; 600 return QueuePtr; 740 return ArgInfo.QueuePtr.getRegister();
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H A D | AMDGPUArgumentUsageInfo.h | 126 ArgDescriptor QueuePtr; member in struct:llvm::AMDGPUFunctionArgInfo
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H A D | AMDGPUTargetMachine.cpp | 1107 parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass, 1108 MFI->ArgInfo.QueuePtr, 2, 0) ||
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H A D | AMDGPULegalizerInfo.cpp | 1221 Register QueuePtr = MRI.createGenericVirtualRegister( 1225 if (!loadInputValue(QueuePtr, B, &MFI->getArgInfo().QueuePtr)) 1245 B.materializePtrAdd(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
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H A D | SIISelLowering.cpp | 1743 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo); 4636 SDValue QueuePtr = CreateLiveInRegister( local 4640 QueuePtr, SDValue()); 4700 SDValue QueuePtr = CreateLiveInRegister( local 4707 SDValue Ptr = DAG.getObjectPtrOffset(DL, QueuePtr, StructOffset); 4713 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
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