Searched refs:PLL (Results 1 - 2 of 2) sorted by relevance
| /freebsd-11-stable/sys/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 119 #define PLL(_id, cname, pname) \ macro
221 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
232 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
245 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
258 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
269 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
280 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
293 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
303 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
313 PLL(TEGRA124_CLK_PLL_
[all...] |
| /freebsd-11-stable/sys/arm/allwinner/clk/ |
| H A D | aw_pll.c | 30 * Allwinner PLL clock
352 /* Allow changing PLL frequency while enabled */
355 /* Set PLL to 297MHz */
606 /* Wait for PLL to become stable */
666 #define PLL(_type, _recalc, _set_freq, _init) \ macro
674 PLL(AWPLL_A10_PLL1, a10_pll1_recalc, NULL, NULL),
675 PLL(AWPLL_A10_PLL2, a10_pll2_recalc, a10_pll2_set_freq, NULL),
676 PLL(AWPLL_A10_PLL3, a10_pll3_recalc, a10_pll3_set_freq, a10_pll3_init),
677 PLL(AWPLL_A10_PLL5, a10_pll5_recalc, NULL, NULL),
678 PLL(AWPLL_A10_PLL
[all...] |
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