/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsMCInstLower.h | 37 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 45 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const; 46 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, 48 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
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H A D | MipsMCInstLower.cpp | 215 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const { 216 OutMI.setOpcode(Mips::LUi); 219 OutMI.addOperand(LowerOperand(MI->getOperand(0))); 244 OutMI.addOperand(MCOperand::createExpr(MipsExpr)); 247 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), 253 MCInst &OutMI, int Opcode) const { 254 OutMI.setOpcode(Opcode); 278 OutMI.addOperand(LowerOperand(MO)); 286 OutMI.addOperand(MCOperand::createExpr(MipsExpr)); 289 OutMI 252 lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMCInstLower.cpp | 47 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 48 OutMI.setOpcode(MI->getOpcode()); 81 OutMI.addOperand(MCOp);
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H A D | BPFMCInstLower.h | 34 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEMCInstLower.cpp | 58 void llvm::LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, argument 60 OutMI.setOpcode(MI->getOpcode()); 67 OutMI.addOperand(MCOp);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcMCInstLower.cpp | 94 MCInst &OutMI, 98 OutMI.setOpcode(MI->getOpcode()); 105 OutMI.addOperand(MCOp); 93 LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZMCInstLower.h | 31 // Lower MachineInstr MI to MCInst OutMI. 32 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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H A D | SystemZMCInstLower.cpp | 94 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { 95 OutMI.setOpcode(MI->getOpcode()); 100 OutMI.addOperand(lowerOperand(MO));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreMCInstLower.h | 31 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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H A D | XCoreMCInstLower.cpp | 103 void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 104 OutMI.setOpcode(MI->getOpcode()); 111 OutMI.addOperand(MCOp);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCMCInstLower.h | 33 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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H A D | ARCMCInstLower.cpp | 104 void ARCMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 105 OutMI.setOpcode(MI->getOpcode()); 112 OutMI.addOperand(MCOp);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRMCInstLower.h | 31 void lowerInstruction(const MachineInstr &MI, MCInst &OutMI) const;
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H A D | AVRMCInstLower.cpp | 62 void AVRMCInstLower::lowerInstruction(const MachineInstr &MI, MCInst &OutMI) const { 63 OutMI.setOpcode(MI.getOpcode()); 106 OutMI.addOperand(MCOp);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyMCInstLower.cpp | 45 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI); 207 MCInst &OutMI) const { 208 OutMI.setOpcode(MI->getOpcode()); 304 OutMI.addOperand(MCOp); 308 removeRegisterOperands(MI, OutMI); 311 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI) { argument 329 auto RegOpcode = OutMI.getOpcode(); 332 OutMI.setOpcode(StackOpcode); 335 for (auto I = OutMI.getNumOperands(); I; --I) { 336 auto &MO = OutMI [all...] |
H A D | WebAssemblyMCInstLower.h | 43 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUMCInstLower.cpp | 56 void lower(const MachineInstr *MI, MCInst &OutMI) const; 66 void lower(const MachineInstr *MI, MCInst &OutMI) const; 176 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { 188 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); 192 OutMI.addOperand(Dest); 193 OutMI.addOperand(Src); 207 OutMI.setOpcode(MCOpcode); 212 OutMI.addOperand(MCOp); 216 if (FIIdx >= (int)OutMI.getNumOperands()) 217 OutMI [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiMCInstLower.cpp | 93 void LanaiMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 94 OutMI.setOpcode(MI->getOpcode()); 136 OutMI.addOperand(MCOp);
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H A D | LanaiMCInstLower.h | 34 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430MCInstLower.cpp | 115 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 116 OutMI.setOpcode(MI->getOpcode()); 157 OutMI.addOperand(MCOp);
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H A D | MSP430MCInstLower.h | 33 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVMCInstLower.cpp | 128 void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, argument 130 OutMI.setOpcode(MI->getOpcode()); 135 OutMI.addOperand(MCOp);
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H A D | RISCV.h | 33 void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64MCInstLower.h | 38 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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H A D | AArch64MCInstLower.cpp | 296 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 297 OutMI.setOpcode(MI->getOpcode()); 302 OutMI.addOperand(MCOp); 305 switch (OutMI.getOpcode()) { 307 OutMI = MCInst(); 308 OutMI.setOpcode(AArch64::RET); 309 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); 312 OutMI = MCInst(); 313 OutMI.setOpcode(AArch64::RET); 314 OutMI [all...] |