Searched refs:Opc (Results 1 - 25 of 257) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Utils/
H A DRISCVMatInt.h21 unsigned Opc; member in struct:llvm::RISCVMatInt::Inst
24 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} argument
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCSEConfigBase.h23 virtual bool shouldCSEOpc(unsigned Opc) { return false; } argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp47 unsigned Opc = MI.getOpcode(); local
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
69 unsigned Opc = MI.getOpcode(); local
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
72 (Opc
87 unsigned Opc = 0, ZeroReg = 0; local
252 unsigned Opc = 0; local
325 unsigned Opc = 0; local
406 unsigned Opc; local
591 unsigned Opc = ABI.GetPtrAdduOp(); local
696 compareOpndSize(unsigned Opc, const MachineFunction &MF) const argument
[all...]
H A DMips16InstrInfo.cpp73 unsigned Opc = 0; local
77 Opc = Mips::MoveR3216;
80 Opc = Mips::Move32R16;
83 Opc = Mips::Mfhi16, SrcReg = 0;
86 Opc = Mips::Mflo16, SrcReg = 0;
88 assert(Opc && "Cannot copy registers");
90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
115 unsigned Opc = 0; local
117 Opc = Mips::SwRxSpImmX16;
118 assert(Opc
133 unsigned Opc = 0; local
219 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; local
249 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? local
[all...]
H A DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst
22 Inst(unsigned Opc, unsigned ImmOpnd);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h112 // Return the non-pre/post incrementing version of 'Opc'. Return 0
114 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
487 bool isUncondBranchOpcode(int Opc) { argument
488 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
512 static inline bool isVPTOpcode(int Opc) { argument
513 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
514 Opc
619 isCondBranchOpcode(int Opc) argument
623 isJumpTableBranchOpcode(int Opc) argument
630 isIndirectBranchOpcode(int Opc) argument
634 isPopOpcode(int Opc) argument
640 isPushOpcode(int Opc) argument
[all...]
H A DARMInstrInfo.h30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
32 unsigned getUnindexedOpcode(unsigned Opc) const override;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp748 unsigned Opc;
752 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
755 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_shared_yes_6432
760 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_const_yes_6432
765 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_local_yes_6432
770 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0),
777 unsigned Opc;
781 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
785 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_to_shared_yes_3264
790 Opc
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DConstantFoldingMIRBuilder.h28 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
31 switch (Opc) {
53 ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI()))
64 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
69 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps);
H A DCSEMIRBuilder.h54 bool canPerformCSEForOpc(unsigned Opc) const;
70 void profileMBBOpcode(GISelInstProfileBuilder &B, unsigned Opc) const;
72 void profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp51 bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const {
53 if (!CSEInfo || !CSEInfo->shouldCSE(Opc))
83 unsigned Opc) const {
87 B.addNodeIDOpcode(Opc);
90 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, argument
95 profileMBBOpcode(B, Opc);
137 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
141 switch (Opc) {
160 if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(),
172 ConstantFoldExtOp(Opc, Src
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H A DCSEInfo.cpp36 bool CSEConfigFull::shouldCSEOpc(unsigned Opc) { argument
37 switch (Opc) {
66 bool CSEConfigConstantOnly::shouldCSEOpc(unsigned Opc) { argument
67 return Opc == TargetOpcode::G_CONSTANT;
164 void GISelCSEInfo::countOpcodeHit(unsigned Opc) { argument
166 if (OpcodeHitTable.count(Opc))
167 OpcodeHitTable[Opc] += 1;
169 OpcodeHitTable[Opc] = 1;
218 bool GISelCSEInfo::shouldCSE(unsigned Opc) const {
220 if (!isPreISelGenericOpcode(Opc))
[all...]
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DConversionChecker.cpp78 BinaryOperator::Opcode Opc = B->getOpcode(); local
79 if (Opc == BO_Assign) {
82 } else if (Opc == BO_AddAssign || Opc == BO_SubAssign) {
85 } else if (Opc == BO_MulAssign) {
88 } else if (Opc == BO_DivAssign || Opc == BO_RemAssign) {
91 } else if (Opc == BO_AndAssign) {
94 } else if (Opc == BO_OrAssign || Opc
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp148 unsigned Opc = I->getOpcode(); local
149 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
210 unsigned Opc = MII->getOpcode(); local
211 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
212 Opc == PPC::BDZ8 || Opc == PPC::BDZ)
H A DPPCPreEmitPeephole.cpp83 unsigned Opc = BBI->getOpcode(); local
84 if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS &&
85 Opc != PPC::LIS8)
124 if (AfterBBI->getOpcode() != Opc)
186 unsigned Opc = MI.getOpcode(); variable
187 if (Opc == PPC::UNENCODED_NOP) {
192 if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) {
193 const MCInstrDesc &MCID = TII->get(Opc);
[all...]
H A DPPCFastISel.cpp113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
457 unsigned Opc; local
482 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
485 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
489 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
491 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
495 Opc = PPC::LD;
501 Opc = PPCSubTarget->hasSPE() ? PPC::SPELWZ : PPC::LFS;
504 Opc
626 unsigned Opc; local
1090 unsigned Opc; local
1134 unsigned Opc; local
1226 unsigned Opc; local
1286 unsigned Opc; local
1813 unsigned Opc; local
2016 unsigned Opc; local
2223 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; local
2378 fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp386 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 local
388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
605 unsigned Opc = local
607 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
624 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 local
626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
659 unsigned Opc; local
666 Opc = WebAssembly::ARGUMENT_i32;
670 Opc = WebAssembly::ARGUMENT_i64;
674 Opc
762 unsigned Opc; local
906 unsigned Opc; local
1003 unsigned Opc; local
1072 unsigned Opc; local
1169 unsigned Opc; local
1225 unsigned Opc; local
1285 unsigned Opc = WebAssembly::BR_IF; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DWebAssemblyDisassemblerEmitter.cpp37 auto Opc = static_cast<unsigned>( local
40 if (Opc == 0xFFFFFFFF)
42 assert(Opc <= 0xFFFF);
43 auto Prefix = Opc >> 8;
44 Opc = Opc & 0xFF;
45 auto &CGIP = OpcodeTable[Prefix][Opc];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp158 static unsigned getBranchDisplacementBits(unsigned Opc) { argument
159 switch (Opc) {
439 unsigned Opc = 0; local
456 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
466 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr;
484 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr;
490 assert(Opc && SrcOpNum && "Missing parameters");
494 return Opc;
623 unsigned Opc = 0; local
628 Opc
887 unsigned Opc = MI.getOpcode(); local
1196 unsigned Opc = CmpInstr.getOpcode(); local
1718 isUnscaledLdSt(unsigned Opc) argument
1743 getUnscaledLdSt(unsigned Opc) argument
1773 getLoadStoreImmIdx(unsigned Opc) argument
1838 convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit) argument
2241 getMemScale(unsigned Opc) argument
2305 scaleOffset(unsigned Opc, int64_t &Offset) argument
2855 unsigned Opc = 0; local
2997 unsigned Opc = 0; local
3106 emitFrameOffsetAdj(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int64_t Offset, unsigned Opc, const TargetInstrInfo *TII, MachineInstr::MIFlag Flag, bool NeedsWinCFI, bool *HasWinCFI) argument
3211 unsigned Opc = SetNZCV ? AArch64::ADDSXri : AArch64::ADDXri; local
3740 unsigned Opc = Root.getOpcode(); local
4369 unsigned Opc; local
5316 unsigned Opc = (Imm < 32) local
[all...]
H A DAArch64InstrInfo.h83 static bool isUnscaledLdSt(unsigned Opc);
90 static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
93 static int getMemScale(unsigned Opc);
100 static unsigned getLoadStoreImmIdx(unsigned Opc);
107 static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
128 /// Returns true if opcode \p Opc is a memory operation. If it is, set
352 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } argument
354 static inline bool isCondBranchOpcode(int Opc) { argument
355 switch (Opc) {
371 isIndirectBranchOpcode(int Opc) argument
[all...]
H A DAArch64ConditionOptimizer.cpp217 static int getComplementOpc(int Opc) { argument
218 switch (Opc) {
244 unsigned Opc = CmpMI->getOpcode(); local
248 bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);
263 Opc = getComplementOpc(Opc);
266 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
273 unsigned Opc; local
275 std::tie(Imm, Opc, Cm
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.h150 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { argument
151 switch (Opc) {
364 inline unsigned GetDefaultP2Align(unsigned Opc) { argument
365 auto Align = GetDefaultP2AlignAny(Opc);
372 inline bool isArgument(unsigned Opc) { argument
373 switch (Opc) {
402 inline bool isCopy(unsigned Opc) { argument
403 switch (Opc) {
422 inline bool isTee(unsigned Opc) { argument
423 switch (Opc) {
442 isCallDirect(unsigned Opc) argument
476 isCallIndirect(unsigned Opc) argument
512 getCalleeOpNo(unsigned Opc) argument
573 isMarker(unsigned Opc) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DXRayInstrumentation.cpp96 unsigned Opc = 0; local
101 Opc = TargetOpcode::PATCHABLE_RET;
106 Opc = TargetOpcode::PATCHABLE_TAIL_CALL;
108 if (Opc != 0) {
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc))
129 unsigned Opc = 0; local
132 Opc = TargetOpcode::PATCHABLE_FUNCTION_EXIT;
135 Opc = TargetOpcode::PATCHABLE_TAIL_CALL;
137 if (Opc != 0) {
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc));
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp138 unsigned Opc = ARC::SUB_rrlimm; local
140 Opc = ARC::SUB_rru6;
142 Opc = ARC::SUB_rrs12;
143 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP)
255 unsigned Opc = ARC::SUB_rrlimm; local
257 Opc = ARC::SUB_rru6;
258 BuildMI(MBB, MBBI, DebugLoc(), TII->get(Opc), ARC::SP)
283 unsigned Opc = ARC::ADD_rrlimm; local
285 Opc = ARC::ADD_rru6;
287 Opc
298 unsigned Opc = ARC::ADD_rrlimm; local
325 unsigned Opc = ARC::ADD_rrlimm; local
456 unsigned Opc; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp61 static bool IsConditionalBranch(int Opc) { argument
62 switch (Opc) {
76 static bool IsUnconditionalJump(int Opc) { argument
77 return (Opc == Hexagon::J2_jump);
128 int Opc = MI.getOpcode(); local
129 if (IsConditionalBranch(Opc)) {

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