Searched refs:OpLo (Results 1 - 5 of 5) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp75 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
142 expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) {
154 buildMI(MBB, MBBI, OpLo)
328 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
336 OpLo = AVR::SBCIRdK;
340 auto MIBLO = buildMI(MBB, MBBI, OpLo)
391 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
396 OpLo = AVR::COMRd;
400 auto MIBLO = buildMI(MBB, MBBI, OpLo)
421 unsigned OpLo, OpH local
454 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; local
489 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
538 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
582 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
631 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
662 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
693 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
748 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
971 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg; local
1017 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg; local
1045 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg; local
1079 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg; local
1113 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg; local
1147 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
1177 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg; local
1208 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg; local
1233 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
1337 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
1370 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
1413 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
1539 unsigned OpLo, OpHi, DstLoReg, DstHiReg; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1275 SDValue OpLo = Op; local
1283 GetSplitVector(Op, OpLo, OpHi);
1285 std::tie(OpLo, OpHi) = DAG.SplitVectorOperand(N, i);
1288 OpsLo[i] = OpLo;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp1963 const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3); local
1966 RegisterSubReg SrcRL(OpLo), SrcRH(OpHi);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp3980 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo, local
3985 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4003 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, local
4008 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4026 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2, local
4031 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp19619 SDValue OpLo = DAG.getNode(ExtendInVecOpc, dl, HalfVT, In);
19625 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpLo);
19633 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
19986 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
19990 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
19993 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
20016 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
20022 OpLo
[all...]

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