/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 70 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, 76 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 82 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, 88 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 94 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, 101 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, 107 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 113 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 119 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, 124 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, 212 getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 233 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 259 getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 295 getCondBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 317 getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 337 getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 346 getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 365 getTestBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 387 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 415 getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 439 getFixedPointScaleOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 448 getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 457 getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 466 getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 475 getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 484 getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 493 getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 502 getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 511 getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 520 getImm8OptLsl(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 538 getSVEIncDecImm(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 549 getMoveVecShifterOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 93 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 231 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 597 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 626 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument 664 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 677 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 689 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 701 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 713 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 742 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 756 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 772 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 787 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 799 getThumbBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 829 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 870 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 890 getITMaskOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 917 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 930 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &, const MCSubtargetInfo &STI) const argument 946 getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 980 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1031 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1062 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelector.cpp | 37 MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, 45 I.getOperand(OpIdx), OpIdx); 36 constrainOperandRegToRegClass( MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const argument
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H A D | RegisterBankInfo.cpp | 113 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, 119 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); 124 Register Reg = MI.getOperand(OpIdx).getReg(); 183 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; 184 ++OpIdx) { 185 const MachineOperand &MO = MI.getOperand(OpIdx); 204 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, MRI); 233 for (; OpIdx != EndIdx; ++OpIdx) { 112 getRegBankFromConstraints( const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const argument 662 getVRegsMem(unsigned OpIdx) argument 698 createVRegs(unsigned OpIdx) argument [all...] |
H A D | CallLowering.cpp | 78 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx, argument 83 if (Attrs.hasAttribute(OpIdx, Attribute::ZExt)) 85 if (Attrs.hasAttribute(OpIdx, Attribute::SExt)) 87 if (Attrs.hasAttribute(OpIdx, Attribute::InReg)) 89 if (Attrs.hasAttribute(OpIdx, Attribute::StructRet)) 91 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftSelf)) 93 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftError)) 95 if (Attrs.hasAttribute(OpIdx, Attribute::ByVal)) 97 if (Attrs.hasAttribute(OpIdx, Attribute::InAlloca)) 103 auto Ty = Attrs.getAttribute(OpIdx, Attribut [all...] |
H A D | RegBankSelect.cpp | 467 for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands(); 468 OpIdx != EndOpIdx; ++OpIdx) { 469 const MachineOperand &MO = MI.getOperand(OpIdx); 475 LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n'); 477 InstrMapping.getOperandMapping(OpIdx); 486 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, 493 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); 594 unsigned OpIdx = RepairPt.getOpIdx(); local 595 MachineOperand &MO = MI.getOperand(OpIdx); 723 RepairingPlacement( MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, RepairingPlacement::RepairingKind Kind) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/ |
H A D | GIMatchTree.h | 28 Optional<unsigned> OpIdx; member in class:llvm::GIMatchTreeVariableBinding 32 Optional<unsigned> OpIdx = None) 33 : Name(Name), InstrID(InstrID), OpIdx(OpIdx) {} 35 bool isInstr() const { return !OpIdx.hasValue(); } 39 assert(OpIdx.hasValue() && "Is not an operand binding"); 40 return *OpIdx; 92 void bindOperandVariable(StringRef Name, unsigned InstrID, unsigned OpIdx) { argument 93 VarBindings.emplace_back(Name, InstrID, OpIdx); 215 /// Record information that is known about the operand bound to this ID, OpIdx, 226 unsigned OpIdx; member in class:llvm::GIMatchTreeOperandInfo 229 GIMatchTreeOperandInfo(const GIMatchDagInstr *InstrNode, unsigned OpIdx) argument 591 unsigned OpIdx; member in class:llvm::GIMatchTreeVRegDefPartitioner 599 GIMatchTreeVRegDefPartitioner(unsigned InstrID, unsigned OpIdx) argument 608 << "].getOperand(" << OpIdx << "))"; variable [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | BreakFalseDeps.cpp | 81 bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, 86 bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref); 107 bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, argument 109 MachineOperand &MO = MI->getOperand(OpIdx); 126 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF); 163 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, argument 165 Register reg = MI->getOperand(OpIdx).getReg(); 230 unsigned OpIdx = UndefReads.back().second; local 237 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) 238 TII->breakPartialRegDependency(*UndefMI, OpIdx, TR [all...] |
H A D | MachineInstr.cpp | 783 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, argument 786 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 789 if (OpIdx < InlineAsm::MIOp_FirstOperand) 801 if (i + NumOps > OpIdx) { 831 MachineInstr::getRegClassConstraint(unsigned OpIdx, 840 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 842 if (!getOperand(OpIdx).isReg()) 847 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, 887 getRegClassConstraintEffectForVRegImpl( unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const argument 899 getRegClassConstraintEffect( unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | InstructionSelectorImpl.h | 88 int64_t OpIdx = MatchTable[CurrentIdx++]; local 94 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 120 << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx local 186 int64_t OpIdx = MatchTable[CurrentIdx++]; local 192 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 196 << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", " 471 int64_t OpIdx = MatchTable[CurrentIdx++]; local 482 << ", OpIdx=" << OpIdx << ")\n"); local 485 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); 520 int64_t OpIdx = MatchTable[CurrentIdx++]; local 537 int64_t OpIdx = MatchTable[CurrentIdx++]; local 568 int64_t OpIdx = MatchTable[CurrentIdx++]; local 588 int64_t OpIdx = MatchTable[CurrentIdx++]; local 612 int64_t OpIdx = MatchTable[CurrentIdx++]; local 637 int64_t OpIdx = MatchTable[CurrentIdx++]; local 659 int64_t OpIdx = MatchTable[CurrentIdx++]; local 674 int64_t OpIdx = MatchTable[CurrentIdx++]; local 689 int64_t OpIdx = MatchTable[CurrentIdx++]; local 692 << "]->getOperand(" << OpIdx << "))\\n"); local 702 int64_t OpIdx = MatchTable[CurrentIdx++]; local 705 << "]->getOperand(" << OpIdx << "))\\n"); local 727 int64_t OpIdx = MatchTable[CurrentIdx++]; local 784 int64_t OpIdx = MatchTable[CurrentIdx++]; local 790 << "], MIs[" << OldInsnID << "], " << OpIdx << ")\\n"); local 797 int64_t OpIdx = MatchTable[CurrentIdx++]; local 815 int64_t OpIdx = MatchTable[CurrentIdx++]; local 963 int64_t OpIdx = MatchTable[CurrentIdx++]; local 980 int64_t OpIdx = MatchTable[CurrentIdx++]; local [all...] |
H A D | LegalizerHelper.h | 99 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a 103 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx, 106 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a 109 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx); 111 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a 114 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0, 117 // Legalize a single operand \p OpIdx of the machine instruction \p MI as a 120 void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx, 122 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a 125 void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx); [all...] |
H A D | RegisterBankInfo.h | 280 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the 281 /// OpIdx-th operand starts. -1 means we do not have such mapping yet. 302 /// values for the \p OpIdx-th operand. 306 /// \pre getMI().getOperand(OpIdx).isReg() 308 getVRegsMem(unsigned OpIdx); 338 /// OpIdx-th operand. 345 /// \pre getMI().getOperand(OpIdx).isReg() 347 /// \post All the partial mapping of the \p OpIdx-th operand have been 349 void createVRegs(unsigned OpIdx); 352 /// the OpIdx [all...] |
H A D | Utils.h | 50 /// Constrain the Register operand OpIdx, so that it is now constrained to the 64 const MachineOperand &RegMO, unsigned OpIdx); 66 /// Try to constrain Reg so that it is usable by argument OpIdx of the 81 const MachineOperand &RegMO, unsigned OpIdx);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MIRFormatter.h | 36 /// None to OpIdx means the index is unknown. 38 Optional<unsigned> OpIdx, int64_t Imm) const { 44 virtual bool parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, argument 37 printImm(raw_ostream &OS, const MachineInstr &MI, Optional<unsigned> OpIdx, int64_t Imm) const argument
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H A D | MachineInstr.h | 461 /// Return true if operand \p OpIdx is a subregister index. 462 bool isOperandSubregIdx(unsigned OpIdx) const { 463 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && 465 if (isExtractSubreg() && OpIdx == 2) 467 if (isInsertSubreg() && OpIdx == 3) 469 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) 471 if (isSubregToReg() && OpIdx == 3) 1297 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if 1298 /// getOperand(OpIdx) doe [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64StackTaggingPreRA.cpp | 179 unsigned OpIdx = TII->getLoadStoreImmIdx(UseI->getOpcode()) - 1; local 180 if (UseI->getOperand(OpIdx).isReg() && 181 UseI->getOperand(OpIdx).getReg() == TaggedReg) { 182 UseI->getOperand(OpIdx).ChangeToFrameIndex(FI); 183 UseI->getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED);
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H A D | AArch64PromoteConstant.cpp | 253 /// Check if the given use (Instruction + OpIdx) of Cst should be converted into 259 unsigned OpIdx) { 262 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) 266 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) 270 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) 273 if (isa<const AllocaInst>(Instr) && OpIdx > 0) 277 if (isa<const LoadInst>(Instr) && OpIdx > 0) 281 if (isa<const StoreInst>(Instr) && OpIdx > 1) 285 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) 258 shouldConvertUse(const Constant *Cst, const Instruction *Instr, unsigned OpIdx) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRInstPrinter.h | 46 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeEmitterGen.cpp | 105 unsigned OpIdx; local 106 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { 108 OpIdx = CGI.Operands[OpIdx].MIOperandNo; 109 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && 132 OpIdx = NumberedOp++; 135 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); 150 Case += " " + EncoderMethodName + "(MI, " + utostr(OpIdx); 153 Case += " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); 160 Case += " getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) 301 unsigned OpIdx; local [all...] |
H A D | GlobalISelEmitter.cpp | 753 /// The representative condition, with a type and a path (InsnVarID and OpIdx 1088 unsigned OpIdx; member in class:__anon2930::PredicateMatcher 1091 PredicateMatcher(PredicateKind Kind, unsigned InsnVarID, unsigned OpIdx = ~0) 1092 : Kind(Kind), InsnVarID(InsnVarID), OpIdx(OpIdx) {} 1095 unsigned getOpIdx() const { return OpIdx; } 1106 OpIdx == B.OpIdx; 1133 unsigned OpIdx) 1134 : PredicateMatcher(Kind, InsnVarID, OpIdx) {} 1132 OperandPredicateMatcher(PredicateKind Kind, unsigned InsnVarID, unsigned OpIdx) argument 1155 SameOperandMatcher(unsigned InsnVarID, unsigned OpIdx, StringRef MatchingName) argument 1188 LLTOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const LLTCodeGen &Ty) argument 1240 PointerToAnyOperandMatcher(unsigned InsnVarID, unsigned OpIdx, unsigned SizeInBits) argument 1270 ComplexPatternOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const OperandMatcher &Operand, const Record &TheDef) argument 1302 RegisterBankOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const CodeGenRegisterClass &RC) argument 1329 MBBOperandMatcher(unsigned InsnVarID, unsigned OpIdx) argument 1346 ImmOperandMatcher(unsigned InsnVarID, unsigned OpIdx) argument 1368 ConstantIntOperandMatcher(unsigned InsnVarID, unsigned OpIdx, int64_t Value) argument 1396 LiteralIntOperandMatcher(unsigned InsnVarID, unsigned OpIdx, int64_t Value) argument 1424 CmpPredicateOperandMatcher(unsigned InsnVarID, unsigned OpIdx, std::string P) argument 1454 IntrinsicIDOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const CodeGenIntrinsic *II) argument 1482 unsigned OpIdx; member in class:__anon2930::OperandMatcher 1491 OperandMatcher(InstructionMatcher &Insn, unsigned OpIdx, const std::string &SymbolicName, unsigned AllocatedTemporariesBaseID) argument 1535 CommentOS << "Operand " << OpIdx; local 1963 unsigned OpIdx; member in class:MemoryVsLLTSizePredicateMatcher 1966 MemoryVsLLTSizePredicateMatcher(unsigned InsnVarID, unsigned MMOIdx, enum RelationKind Relation, unsigned OpIdx) argument 2072 addOperand(unsigned OpIdx, const std::string &SymbolicName, unsigned AllocatedTemporariesBaseID) argument 2082 getOperand(unsigned OpIdx) argument 2092 addPhysRegInput(Record *Reg, unsigned OpIdx, unsigned TempOpIdx) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInstructionSelector.h | 174 int OpIdx = -1) const; 177 int OpIdx) const; 180 int OpIdx) const; 183 int OpIdx) const; 186 int OpIdx) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
H A D | MCInstPrinter.cpp | 63 const MCRegisterInfo &MRI, unsigned &OpIdx, 73 const MCOperand &Opnd = MI.getOperand(OpIdx); 74 ++OpIdx; 127 unsigned OpIdx = 0; local 129 return matchAliasCondition(*MI, STI, MRI, OpIdx, M, C); 62 matchAliasCondition(const MCInst &MI, const MCSubtargetInfo *STI, const MCRegisterInfo &MRI, unsigned &OpIdx, const AliasMatchingData &M, const AliasPatternCond &C) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZHazardRecognizer.cpp | 122 for (unsigned OpIdx = 0; OpIdx < MID.getNumOperands(); OpIdx++) { 123 const TargetRegisterClass *RC = TII->getRegClass(MID, OpIdx, TRI, MF); 126 if (OpIdx >= MID.getNumDefs() && 127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430InstPrinter.h | 31 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcInstPrinter.h | 38 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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