Searched refs:NumVecs (Results 1 - 6 of 6) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp206 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
213 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
215 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
217 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
218 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
220 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
221 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
222 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
223 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1164 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigne argument
1279 SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1305 SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1337 SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1357 SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1413 SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1452 SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1507 SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1536 SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
[all...]
H A DAArch64ISelLowering.cpp11657 unsigned NumVecs = 0; local
11662 NumVecs = 2; break;
11664 NumVecs = 3; break;
11666 NumVecs = 4; break;
11668 NumVecs = 2; IsStore = true; break;
11670 NumVecs = 3; IsStore = true; break;
11672 NumVecs = 4; IsStore = true; break;
11674 NumVecs = 2; break;
11676 NumVecs = 3; break;
11678 NumVecs
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp193 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
196 /// For NumVecs <= 2, QOpcodes1 is not used.
197 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
201 /// SelectVST - Select NEON store intrinsics. NumVecs should
204 /// For NumVecs <= 2, QOpcodes1 is not used.
205 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
209 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
213 unsigned NumVecs, const uint16_t *DOpcodes,
261 /// SelectMVE_VLD - Select MVE interleaving load intrinsics. NumVecs
264 /// pointer points to a set of NumVecs su
1867 GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs, bool is64BitVector) argument
2003 isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) argument
2008 SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument
2147 SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument
2298 SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes) argument
2646 SelectMVE_VLD(SDNode *N, unsigned NumVecs, const uint16_t *const *Opcodes) argument
2687 SelectVLDDup(SDNode *N, bool IsIntrinsic, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument
[all...]
H A DARMISelLowering.cpp13108 unsigned NumVecs = 0; local
13114 NumVecs = 1; break;
13116 NumVecs = 2; break;
13118 NumVecs = 3; break;
13120 NumVecs = 4; break;
13128 NumVecs = 2; isLaneOp = true; break;
13130 NumVecs = 3; isLaneOp = true; break;
13132 NumVecs = 4; isLaneOp = true; break;
13134 NumVecs = 1; isLoadOp = false; break;
13136 NumVecs
13312 unsigned NumVecs = 0; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp669 unsigned NumVecs) {
672 for (unsigned j = 0; j < NumVecs; j++)
727 unsigned NumVecs = Vecs.size(); local
728 assert(NumVecs > 1 && "Should be at least two vectors");
734 for (unsigned i = 0; i < NumVecs - 1; i += 2) {
736 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
743 if (NumVecs % 2 != 0)
744 TmpList.push_back(ResList[NumVecs - 1]);
747 NumVecs = ResList.size();
748 } while (NumVecs >
668 createInterleaveMask(IRBuilder< &Builder, unsigned VF, unsigned NumVecs) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h327 /// This function creates a shuffle mask for interleaving \p NumVecs vectors of
331 /// <0, VF, VF * 2, ..., VF * (NumVecs - 1), 1, VF + 1, VF * 2 + 1, ...>
333 /// For example, the mask for VF = 4 and NumVecs = 2 is:
337 unsigned NumVecs);

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