/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 136 BinaryOperator *NewShift = BinaryOperator::Create(ShiftOpcode, X, NewShAmt); local 143 NewShift->setHasNoUnsignedWrap(Sh0->hasNoUnsignedWrap() && 145 NewShift->setHasNoSignedWrap(Sh0->hasNoSignedWrap() && 148 NewShift->setIsExact(Sh0->isExact() && Sh1->isExact()); 152 Instruction *Ret = NewShift; 154 Builder.Insert(NewShift); 155 Ret = CastInst::Create(Instruction::Trunc, NewShift, Sh0->getType()); 310 auto *NewShift = BinaryOperator::Create(OuterShift->getOpcode(), X, local 313 return NewShift; 315 Builder.Insert(NewShift); 850 Value *NewShift = local 867 Value *NewShift = Builder.CreateShl(Op0BO->getOperand(1), Op1); local 894 Value *NewShift = local 913 Value *NewShift = local [all...] |
H A D | InstCombineAddSub.cpp | 1796 Instruction *NewShift = BinaryOperator::CreateAShr(X, ShAmtOp); local 1797 NewShift->copyIRFlags(Op1Wide); 1799 return NewShift; 1800 Builder.Insert(NewShift); 1801 return TruncInst::CreateTruncOrBitCast(NewShift, Op1->getType()); 1808 Instruction *NewShift = BinaryOperator::CreateLShr(X, ShAmtOp); local 1809 NewShift->copyIRFlags(Op1Wide); 1811 return NewShift; 1812 Builder.Insert(NewShift); 1813 return TruncInst::CreateTruncOrBitCast(NewShift, Op [all...] |
H A D | InstCombineCompares.cpp | 1702 Value *NewShift = local 1707 Value *NewAnd = Builder.CreateAnd(Shift->getOperand(0), NewShift);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 3105 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); local 3109 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); 3129 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, local 3132 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); 3139 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, local 3141 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); 3190 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); local 3192 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 1722 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); local 1731 insertDAGNode(DAG, N, NewShift); 1732 DAG.ReplaceAllUsesWith(N, NewShift);
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H A D | X86ISelLowering.cpp | [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 2081 SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt); local 2083 return DAG.getNode(ISD::ADD, DL, VT, NewShift, DAG.getConstant(NewC, DL, VT)); 7368 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), local 7370 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); 7970 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, local 7972 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift); 7980 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, local 7985 SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask);
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