Searched refs:MO2 (Results 1 - 10 of 10) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 102 const MCOperand &MO2 = MI->getOperand(2); local 115 printRegName(O, MO2.getReg()); 125 const MCOperand &MO2 = MI->getOperand(2); local 127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); 385 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 397 printRegName(O, MO2.getReg()); 405 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 410 printRegImmShift(O, ARM_AM::getSORegShOp(MO2 [all...] |
H A D | ARMMCCodeEmitter.cpp | 937 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); local 939 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1255 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1258 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1259 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1260 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1349 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1364 unsigned Imm = MO2.getImm(); 1512 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1513 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86OptimizeLEAs.cpp | 68 const MachineOperand &MO2); 73 const MachineOperand &MO2); 202 const MachineOperand &MO2) { 203 return MO1.isIdenticalTo(MO2) && 215 const MachineOperand &MO2) { 216 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && 218 return (MO1.isImm() && MO2.isImm()) || 219 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || 220 (MO1.isJTI() && MO2 201 isIdenticalOp(const MachineOperand &MO1, const MachineOperand &MO2) argument 214 isSimilarDispOp(const MachineOperand &MO1, const MachineOperand &MO2) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCCodeEmitter.cpp | 127 const MCOperand &MO2 = MI.getOperand(Op + 1); local 128 if (MO2.isImm()) { 130 return ((unsigned)MO2.getImm() << 4) | Reg; 133 assert(MO2.isExpr() && "Expr operand expected"); 146 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1224 MCOperand &MO2) { 1229 TmpInst.addOperand(MO2); 1585 MCOperand &MO2 = Inst.getOperand(2); local 1587 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { 1592 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); 1606 MCOperand &MO2 = Inst.getOperand(2); local 1607 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); 1223 makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, MCOperand &MO2) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 952 MachineOperand &MO2 = Cond[2]; 953 switch (MO2.getReg()) { 955 MO2.setReg(R600::PRED_SEL_ONE); 958 MO2.setReg(R600::PRED_SEL_ZERO);
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H A D | SIInstrInfo.cpp | 417 auto MO2 = *MI2.memoperands_begin(); local 418 if (MO1->getAddrSpace() != MO2->getAddrSpace()) 422 auto Base2 = MO2->getValue();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 452 MCOperand &MO2 = MappedInst.getOperand(2); local 453 MCExpr const *Expr = MO2.getExpr();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineScheduler.cpp | 948 for (const MachineOperand &MO2 : MI.operands()) { 949 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 1004 MachineOperand &MO2 = MI.getOperand(0); local 1007 MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt}); 1008 MO2.setReg(DstExt);
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