/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 134 namespace MCID { namespace in namespace:llvm 257 bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); } 263 bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); } 267 bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); } 271 bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); } 274 bool isReturn() const { return Flags & (1ULL << MCID::Return); } 277 bool isAdd() const { return Flags & (1ULL << MCID::Add); } 280 bool isTrap() const { return Flags & (1ULL << MCID::Trap); } 283 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); } 286 bool isCall() const { return Flags & (1ULL << MCID [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/ |
H A D | CodeEmitter.cpp | 19 CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) { argument 20 EncodingInfo &EI = Encodings[MCID]; 25 const MCInst &Inst = Sequence[MCID]; 26 MCInst Relaxed(Sequence[MCID]);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrBuilder.h | 30 const MCInstrDesc &MCID = MI->getDesc(); local 32 if (MCID.mayLoad()) 34 if (MCID.mayStore())
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/ |
H A D | CodeEmitter.h | 55 EncodingInfo getOrCreateEncodingInfo(unsigned MCID); 63 StringRef getEncoding(unsigned MCID) { argument 64 EncodingInfo EI = getOrCreateEncodingInfo(MCID);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local 30 if (!MCID) 33 if (!MCID->mayLoad()) 55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local 56 if (!MCID) 59 if (!MCID->isBranch()) 85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, argument 90 unsigned IIC = MCID->getSchedClass(); 123 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1) 147 const MCInstrDesc *MCID local 175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local 282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); local [all...] |
H A D | PPCHazardRecognizers.h | 32 bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
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H A D | PPCPreEmitPeephole.cpp | 193 const MCInstrDesc &MCID = TII->get(Opc); variable 194 if (MCID.getNumOperands() == 3 && 203 else if (MCID.getNumOperands() == 2 &&
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 21 const MCInstrDesc &MCID = MI->getDesc(); local 22 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 25 unsigned Opcode = MCID.getOpcode(); 42 const MCInstrDesc &MCID = MI->getDesc(); local 43 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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H A D | Thumb2SizeReduction.cpp | 254 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { argument 255 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) 645 const MCInstrDesc &MCID = MI->getDesc(); local 646 if (MCID.hasOptionalDef() && 647 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) 805 const MCInstrDesc &MCID = MI->getDesc(); local 806 if (MCID.hasOptionalDef()) { 807 unsigned NumOps = MCID.getNumOperands(); 829 unsigned NumOps = MCID.getNumOperands(); 831 if (i < NumOps && MCID 865 const MCInstrDesc &MCID = MI->getDesc(); local [all...] |
H A D | MLxExpansionPass.cpp | 184 const MCInstrDesc &MCID = MI->getDesc(); local 185 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 188 unsigned Opcode = MCID.getOpcode(); 339 const MCInstrDesc &MCID = MI->getDesc(); local 346 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 356 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
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H A D | Thumb2ITBlockPass.cpp | 171 const MCInstrDesc &MCID = MI->getDesc(); local 173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 317 const MCInstrDesc &MCID) { 318 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); 324 const MCInstrDesc &MCID, Register DestReg) { 325 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) 334 const DebugLoc &DL, const MCInstrDesc &MCID, 337 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); 350 const DebugLoc &DL, const MCInstrDesc &MCID, 353 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); 359 const DebugLoc &DL, const MCInstrDesc &MCID, 364 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestRe 316 BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID) argument 323 BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument 332 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument 348 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument 358 BuildMI(MachineBasicBlock &BB, MachineInstr &I, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument 368 BuildMI(MachineBasicBlock &BB, MachineInstr *I, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument 377 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const DebugLoc &DL, const MCInstrDesc &MCID) argument 387 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, const DebugLoc &DL, const MCInstrDesc &MCID) argument 397 BuildMI(MachineBasicBlock &BB, MachineInstr &I, const DebugLoc &DL, const MCInstrDesc &MCID) argument 407 BuildMI(MachineBasicBlock &BB, MachineInstr *I, const DebugLoc &DL, const MCInstrDesc &MCID) argument 415 BuildMI(MachineBasicBlock *BB, const DebugLoc &DL, const MCInstrDesc &MCID) argument 423 BuildMI(MachineBasicBlock *BB, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument [all...] |
H A D | MachineInstr.h | 112 const MCInstrDesc *MCID; // Instruction descriptor. member in class:llvm::MachineInstr 423 const MCInstrDesc &getDesc() const { return *MCID; } 426 unsigned getOpcode() const { return MCID->Opcode; } 442 return getNumExplicitDefs() + MCID->getNumImplicitDefs(); 649 return hasProperty(MCID::PreISelOpcode, Type); 657 return hasProperty(MCID::Variadic, Type); 663 return hasProperty(MCID::HasOptionalDef, Type); 669 return hasProperty(MCID::Pseudo, Type); 673 return hasProperty(MCID::Return, Type); 679 return hasProperty(MCID [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ScoreboardHazardRecognizer.cpp | 122 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local 123 if (!MCID) { 127 unsigned idx = MCID->getSchedClass(); 177 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local 178 assert(MCID && "The scheduler must filter non-machineinstrs"); 179 if (DAG->TII->isZeroCost(MCID->Opcode)) 186 unsigned idx = MCID->getSchedClass();
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H A D | MachineInstr.cpp | 103 if (MCID->ImplicitDefs) 104 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; 107 if (MCID->ImplicitUses) 108 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses; 118 : MCID(&tid), debugLoc(std::move(dl)) { 122 if (unsigned NumOps = MCID->getNumOperands() + 123 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { 135 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) { 200 assert(MCID 1025 const MCInstrDesc &MCID = getDesc(); local [all...] |
H A D | TargetInstrInfo.cpp | 46 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument 49 if (OpNum >= MCID.getNumOperands()) 52 short RegClass = MCID.OpInfo[OpNum].RegClass; 53 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) 160 const MCInstrDesc &MCID = MI.getDesc(); local 161 bool HasDef = MCID.getNumDefs(); 292 const MCInstrDesc &MCID = MI.getDesc(); local 293 if (!MCID.isCommutable()) 298 unsigned CommutableOpIdx1 = MCID.getNumDefs(); 328 const MCInstrDesc &MCID local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXReplaceImageHandles.cpp | 81 const MCInstrDesc &MCID = MI.getDesc(); local 83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { 89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { 95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { 97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); 105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { 112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | ValueMapper.cpp | 86 unsigned MCID : 29; member in struct:__anon130::WorklistEntry 159 unsigned MCID); 163 unsigned MCID); 165 unsigned MCID); 166 void scheduleRemapFunction(Function &F, unsigned MCID); 818 CurrentMCID = E.MCID; 997 unsigned MCID) { 999 assert(MCID < MCs.size() && "Invalid mapping context"); 1003 WE.MCID = MCID; 996 scheduleMapGlobalInitializer(GlobalVariable &GV, Constant &Init, unsigned MCID) argument 1119 scheduleMapGlobalInitializer(GlobalVariable &GV, Constant &Init, unsigned MCID) argument 1125 scheduleMapAppendingVariable(GlobalVariable &GV, Constant *InitPrefix, bool IsOldCtorDtor, ArrayRef<Constant *> NewMembers, unsigned MCID) argument 1134 scheduleMapGlobalIndirectSymbol(GlobalIndirectSymbol &GIS, Constant &Target, unsigned MCID) argument 1140 scheduleRemapFunction(Function &F, unsigned MCID) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ConditionalCompares.cpp | 632 const MCInstrDesc &MCID = TII->get(Opc); local 635 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF)); 637 BuildMI(*Head, Head->end(), TermDL, MCID) 644 TII->getRegClass(MCID, 1, TRI, *MF)); 689 const MCInstrDesc &MCID = TII->get(Opc); local 691 TII->getRegClass(MCID, 0, TRI, *MF)); 694 TII->getRegClass(MCID, 1, TRI, *MF)); 695 MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 202 const MCInstrDesc &MCID = MI->getDesc(); local 204 if (MCID.mayLoad()) 206 if (MCID.mayStore())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGFast.cpp | 254 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local 255 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { 256 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { 261 if (MCID.isCommutable()) 432 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local 433 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); 434 NumRes = MCID.getNumDefs(); 435 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { 511 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local 512 if (!MCID [all...] |
H A D | ScheduleDAGSDNodes.cpp | 212 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 213 for (unsigned I = 0; I != MCID.getNumOperands(); ++I) { 214 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1) 315 const MCInstrDesc &MCID = TII->get(Opc); 316 if (MCID.mayLoad()) 449 const MCInstrDesc &MCID = TII->get(Opc); 450 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { 451 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { 456 if (MCID.isCommutable())
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H A D | ScheduleDAGRRList.cpp | 1034 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local 1035 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { 1036 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { 1041 if (MCID.isCommutable()) 1283 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local 1284 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); 1285 NumRes = MCID.getNumDefs(); 1286 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { 1412 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local 1413 if (MCID [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCChecker.cpp | 87 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); local 92 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) 95 for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i) 96 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue); 99 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) 103 if (Hexagon::R31 != R && MCID.isCall()) 128 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { 182 for (unsigned i = MCID.getNumDefs(); i < MCID [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiDelaySlotFiller.cpp | 229 MCInstrDesc MCID = MI->getDesc(); local 230 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands()
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