/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | InfoByHwMode.cpp | 155 unsigned M0 = Map.begin()->first; local 156 return get(M0) < I.get(M0); 160 unsigned M0 = Map.begin()->first; local 161 return get(M0) == I.get(M0); 165 unsigned M0 = Map.begin()->first; local 166 return get(M0).isSubClassOf(I.get(M0)); 171 unsigned M0 local [all...] |
/freebsd-11-stable/contrib/binutils/opcodes/ |
H A D | ia64-opc-m.c | 24 #define M0 IA64_TYPE_M, 0 macro 80 {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY}, 81 {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY}, 82 {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}, EMPTY}, 83 {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}, EMPTY}, 85 {"invala", M0, OpX3X4X2 (0, 0, 0, 1), {}, EMPTY}, 86 {"fwb", M0, OpX3X4X2 (0, 0, 0, 2), {}, EMPTY}, 87 {"mf", M0, OpX3X4X2 (0, 0, 2, 2), {}, EMPTY}, 88 {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2), {}, EMPTY}, 89 {"srlz.d", M0, OpX3X4X 1091 #undef M0 macro [all...] |
/freebsd-11-stable/crypto/openssl/crypto/md5/asm/ |
H A D | md5-ia64.S | 35 // {in,out}4 Block Value 0 M0 125 #define M0 in4 define 310 // loading into M12 here produces the M0 value, M13 -> M1, etc. 441 // Passed the first 4 words (M0 - M3) and initial (A, B, C, D) values, 542 G(A, B, C, D, M0) \ 543 COMPUTE(A, B, 5, M0, RotateM0) \ 552 H(A, B, C, D, M0) \ 553 COMPUTE(A, B, 4, M0, RotateM0) \ 562 I(A, B, C, D, M0) \ 563 COMPUTE(A, B, 6, M0, RotateM [all...] |
/freebsd-11-stable/contrib/ntp/include/ |
H A D | mbg_gps166.h | 880 l_fp M0; ///< +- Mean Anomaly at Ref. Time [rad] member in struct:__anon4766 926 l_fp M0; ///< +- Mean Anomaly at Ref. Time [rad] member in struct:__anon4767
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 106 cl::desc("Merge and hoist M0 initializations"), 402 // We should almost never get here since we do not usually produce M0 stores 419 // This is intended to combine M0 initializations, but can work with any 620 // Some special instructions use M0 as an input. Some even only use 622 if (DstReg == AMDGPU::M0 && TRI->hasVectorRegisters(SrcRC)) { 694 // Writelane is special in that it can use SGPR and M0 (which would 709 Src0.getReg() != AMDGPU::M0) && 711 Src1.getReg() != AMDGPU::M0)) { 740 // Move src1 to be in M0 742 TII->get(AMDGPU::COPY), AMDGPU::M0) [all...] |
H A D | SIRegisterInfo.cpp | 147 // M0 has to be reserved so that llvm accepts it as a live-in into a block. 148 reserveRegisterTuples(Reserved, AMDGPU::M0); 772 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); 876 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); 1754 if (hasRegUnit(AMDGPU::M0, RegUnit))
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H A D | AMDGPUInstructionSelector.cpp | 1090 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) 1565 // If DS instructions require M0 initializtion, insert it before selecting. 1566 BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0) 1732 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) 1747 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) 1762 .addReg(AMDGPU::M0, RegState::Implicit);
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H A D | SIInstrInfo.cpp | 276 // TODO: ds_consume/ds_append use M0 for the base address. Is it safe to 1072 assert(SrcReg != AMDGPU::M0 && "m0 should not be spilled"); 1201 assert(DestReg != AMDGPU::M0 && "m0 should not be reloaded into"); 3132 return MO.getReg() == AMDGPU::M0 || 3151 case AMDGPU::M0: 3509 if (MO.isReg() && MO.getReg() != AMDGPU::M0) { 3636 if (Soff && Soff->getReg() != AMDGPU::M0) { 6617 if (DstReg == AMDGPU::M0 && SrcReg.isVirtual()) { 6622 if (SrcReg == AMDGPU::M0 && DstReg.isVirtual()) {
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H A D | SIFoldOperands.cpp | 1494 if (CurrentKnownM0Val && MI.modifiesRegister(AMDGPU::M0, TRI)) 1508 if (MI.getOperand(0).getReg() == AMDGPU::M0) {
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H A D | SIISelLowering.cpp | 2991 .Case("m0", AMDGPU::M0) 3013 case AMDGPU::M0: 3211 // Compare the just read M0 value to all possible Idx values. 3242 // Move index from VCC into M0 3244 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) 3247 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) 3383 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) 3386 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) 3426 .addReg(AMDGPU::M0, RegState::Implicit); 3455 .addReg(AMDGPU::M0, RegStat 5137 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue, local 6144 SDValue M0 = M->getOperand(2); local [all...] |
H A D | AMDGPUAsmPrinter.cpp | 712 case AMDGPU::M0:
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H A D | GCNHazardRecognizer.cpp | 855 return SMovRelWaitStates - getWaitStatesSinceDef(AMDGPU::M0, IsHazardFn,
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/freebsd-11-stable/crypto/openssl/crypto/bn/asm/ |
H A D | armv4-mont.pl | 254 my ($Bi,$Ni,$M0)=map("d$_",(28..31)); 279 vld1.32 {${M0}[0]}, [$n0,:32] 293 vmul.u32 $Ni,$temp,$M0 347 vmul.u32 $Ni,$temp,$M0 472 vmul.u32 $Ni,$temp,$M0
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/freebsd-11-stable/crypto/openssl/crypto/ec/asm/ |
H A D | ecp_nistz256-x86_64.pl | 1365 my ($M0,$T0a,$T0b,$T0c,$T0d,$T0e,$T0f,$TMP0)=map("%xmm$_",(8..15)); 1407 movdqa $ONE, $M0 1413 movdqa $M0, $TMP0 1414 paddd $ONE, $M0 1494 movdqa .LOne(%rip), $M0 1502 movdqa $M0, $ONE 1507 movdqa $M0, $TMP0 1508 paddd $ONE, $M0 1556 my ($M0,$T0a,$T0b,$T0c,$TMP0)=map("%ymm$_",(5..9)); 1590 vmovdqa .LOne(%rip), $M0 [all...] |
H A D | ecp_nistz256-avx2.pl | 1919 my ($M0,$T0,$T1,$TMP0)=map("%ymm$_",(12..15)); 1957 vmovdqa (%rax), $M0 1971 vpcmpeqd $INDEX0, $M0, $TMP0 1980 vpcmpeqd $INDEX1, $M0, $TMP0 1989 vpcmpeqd $INDEX2, $M0, $TMP0 1998 vpcmpeqd $INDEX3, $M0, $TMP0 2007 vpaddd (%rax), $M0, $M0 # increment
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/freebsd-11-stable/contrib/ntp/libparse/ |
H A D | data_mbg.c | 443 FETCH_DOUBLE(buffpp, &ephp->M0); 484 FETCH_DOUBLE(buffpp, &almp->M0);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1926 unsigned M0 = N->getMaskElt(0) / 4; local 1936 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) || 1937 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) { 1938 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3]; 1940 Swap = M0 < 4; 1944 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) || 1945 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) { 1952 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) || 1953 (M2 < 4 && M0 2003 unsigned M0 = N->getMaskElt(0) / 4; local 2102 unsigned M0 = N->getMaskElt(0) / 8; local [all...] |
/freebsd-11-stable/contrib/groff/src/preproc/pic/ |
H A D | common.cpp | 110 position M0 = position(rho * cos(phi0), rho * sin(phi0)) + M; local 112 double dist0 = hypot(z0 - M0) / sqrt(z0 * z0);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 651 /* 4 */ P3_0, C5, M0, M1, 706 Register = Hexagon::M0;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenInsert.cpp | 1105 unsigned M0 = BaseOrd[MaxIF.SrcR], M1 = BaseOrd[MaxIF.InsR]; 1107 if (M0 > R0) 1109 if (M0 == R0) {
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H A D | HexagonISelDAGToDAG.cpp | 790 SDValue M0 = CurDAG->getTargetConstant(0x18, dl, MVT::i32); local 793 M0, N->getOperand(2), M1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 1067 const MCOperand &M0 = MI.getOperand(OpIdx); local 1070 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); 1087 const MCOperand &M0 = MI.getOperand(OpIdx); 1090 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 3298 SDValue M0 = peekThroughOneUseTruncation(Mask->getOperand(0)); 3299 if (M0->getOpcode() != ISD::SHL || !checkOneUse(M0)) 3301 if (!isOneConstant(M0->getOperand(0))) 3303 NBits = M0->getOperand(1); 3324 SDValue M0 = peekThroughOneUseTruncation(Mask->getOperand(0)); 3325 if (M0->getOpcode() != ISD::SHL || !checkOneUse(M0)) 3328 if (!isAllOnes(M0->getOperand(0))) 3330 NBits = M0 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 1882 auto LessThan = [](const MergeCandidate* M0, const MergeCandidate *M1) { 1883 return M0->InsertPos < M1->InsertPos;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.cpp | 749 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1061 case 124: return createRegOperand(M0);
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