Searched refs:LogicOp (Results 1 - 5 of 5) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp911 struct LogicOp { struct in namespace:__anon2414
912 LogicOp() = default;
913 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) function in struct:__anon2414::LogicOp
925 static LogicOp interpretAndImmediate(unsigned Opcode) {
927 case SystemZ::NILMux: return LogicOp(32, 0, 16);
928 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
929 case SystemZ::NILL64: return LogicOp(64, 0, 16);
930 case SystemZ::NILH64: return LogicOp(64, 16, 16);
931 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
932 case SystemZ::NIHH64: return LogicOp(6
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2494 SDValue computeLogicOpInGPR(SDValue LogicOp);
2668 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { argument
2669 assert(isLogicOp(LogicOp.getOpcode()) &&
2671 assert(LogicOp.getValueType() == MVT::i1 &&
2673 SDLoc dl(LogicOp);
2677 bool IsBitwiseNegation = isBitwiseNot(LogicOp);
2698 LHS = getLogicOperand(LogicOp.getOperand(0));
2699 RHS = getLogicOperand(LogicOp.getOperand(1));
2716 switch (LogicOp.getOpcode()) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7348 BinaryOperator *LogicOp; local
7350 if (!match(BB.getTerminator(), m_Br(m_OneUse(m_BinOp(LogicOp)), TBB, FBB)))
7363 if (match(LogicOp, m_And(m_OneUse(m_Value(Cond1)),
7366 else if (match(LogicOp, m_Or(m_OneUse(m_Value(Cond1)),
7386 LogicOp->eraseFromParent();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp7236 SDValue LogicOp = Shift->getOperand(0); local
7237 if (!LogicOp.hasOneUse())
7240 unsigned LogicOpcode = LogicOp.getOpcode();
7279 if (matchFirstShift(LogicOp.getOperand(0), X, C0Val))
7280 Y = LogicOp.getOperand(1);
7281 else if (matchFirstShift(LogicOp.getOperand(1), X, C0Val))
7282 Y = LogicOp.getOperand(0);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp20462 unsigned LogicOp = IsFABS ? X86ISD::FAND :
20468 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
20473 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
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