| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 107 /// The lane inserted into is defined by \p LaneIdx. The vector source
111 Register EltReg, unsigned LaneIdx,
153 Register VecReg, unsigned LaneIdx,
1704 unsigned LaneIdx = Offset / 64; local
1707 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB);
2826 emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB);
2830 Src2Reg, /* LaneIdx */ 1, RB, MIB);
2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const {
2933 if (LaneIdx == 0) {
2952 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx);
2900 emitExtractVectorElt( Optional<Register> DstReg, const RegisterBank &DstRB, LLT ScalarTy, Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const argument
2986 unsigned LaneIdx = VRegAndVal->Value; local
3119 unsigned LaneIdx = 1; local
[all...] |
| H A D | AArch64ISelDAGToDAG.cpp | 539 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { argument
554 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
563 SDValue &LaneOp, int &LaneIdx) {
565 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
567 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
583 int LaneIdx = -1; // Will hold the lane index. local
587 LaneIdx)) {
591 LaneIdx))
595 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
626 int LaneIdx; local
562 checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp, SDValue &LaneOp, int &LaneIdx) argument
[all...] |
| H A D | AArch64ISelLowering.cpp | 8079 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); local
8083 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
8138 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); local
8139 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 1695 unsigned LaneIdx = Lane * VWidthPerLane; local
1697 unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum;
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 5513 int64_t LaneIdx;
5524 if (parseSwizzleOperands(1, &LaneIdx,
5527 Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 7377 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); local
7378 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
12930 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); local
12931 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6573 int LaneIdx = (Idx / NumEltsPerLane) * NumEltsPerLane;
6576 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx + 0);
6577 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx + 1);
6580 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx + 0);
6581 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx + 1);
20394 unsigned LaneIdx = LExtIndex / NumEltsPerLane;
20395 X = extract128BitVector(X, LaneIdx * NumEltsPerLane, DAG, DL);
[all...] |