Searched refs:Lane (Results 1 - 25 of 26) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DLaneBitmask.h16 /// Lane masks for sub-register indices are similar to register units for
84 static constexpr LaneBitmask getLane(unsigned Lane) { argument
85 return LaneBitmask(Type(1) << Lane);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
74 unsigned Lane, const TargetRegisterClass *TRC);
88 unsigned Lane, unsigned ToInsert);
419 unsigned Lane, bool QPR) {
425 .addImm(Lane)
434 const DebugLoc &DL, unsigned DReg, unsigned Lane,
441 .addReg(DReg, 0, Lane);
479 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
487 .addImm(Lane);
544 unsigned Lane; local
416 createDupLane(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg, unsigned Lane, bool QPR) argument
432 createExtractSubreg( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
477 createInsertSubreg( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) argument
[all...]
H A DARMBaseInstrInfo.cpp4867 unsigned SReg, unsigned &Lane) {
4869 Lane = 0;
4874 Lane = 1;
4889 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4890 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4898 unsigned Lane, unsigned &ImplicitSReg) {
4908 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4926 unsigned Lane; local
4969 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4971 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 1
4866 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument
4896 getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr &MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) argument
[all...]
H A DARMExpandPseudoInsts.cpp672 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); local
676 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
678 Lane -= RegElts;
680 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
725 MIB.addImm(Lane);
H A DARMISelLowering.cpp7963 int Lane = SVN->getSplatIndex(); local
7965 if (Lane == -1) Lane = 0;
7968 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7974 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
7986 DAG.getConstant(Lane, dl, MVT::i32));
8152 unsigned Lane = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); local
8155 unsigned Mask = ((1 << LaneWidth) - 1) << Lane * LaneWidth;
8166 SDValue Lane = Op.getOperand(2); local
8167 if (!isa<ConstantSDNode>(Lane))
8215 unsigned Lane = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); local
8226 SDValue Lane = Op.getOperand(1); local
14105 SDValue Lane = N0.getOperand(1); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanSLP.cpp316 for (unsigned Lane = 1, E = MultiNodeOps[0].second.size(); Lane < E; ++Lane) {
317 LLVM_DEBUG(dbgs() << " Finding best value for lane " << Lane << "\n");
322 dbgs() << *cast<VPInstruction>(Ops.second[Lane])->getUnderlyingInstr()
324 Candidates.insert(Ops.second[Lane]);
333 VPValue *Last = FinalOrder[Op].second[Lane - 1];
H A DSLPVectorizer.cpp765 /// \returns the operand data at \p OpIdx and \p Lane.
766 OperandData &getData(unsigned OpIdx, unsigned Lane) { argument
767 return OpsVec[OpIdx][Lane];
770 /// \returns the operand data at \p OpIdx and \p Lane. Const version.
771 const OperandData &getData(unsigned OpIdx, unsigned Lane) const {
772 return OpsVec[OpIdx][Lane];
779 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes;
780 ++Lane)
781 OpsVec[OpIdx][Lane]
785 swap(unsigned OpIdx1, unsigned OpIdx2, unsigned Lane) argument
1013 getBestOperand(unsigned OpIdx, int Lane, int LastLane, ArrayRef<ReorderingMode> ReorderingModes) argument
1171 shouldBroadcast(Value *Op, unsigned OpIdx, unsigned Lane) argument
1281 int Lane = FirstLane + Direction * Distance; local
1658 unsigned Lane = 0; local
1723 int Lane; member in struct:llvm::slpvectorizer::ExternalUser
1919 int Lane = -1; member in struct:llvm::slpvectorizer::ScheduleData
2017 int Lane = BundleMember->Lane; local
[all...]
H A DVPlan.cpp164 !(State->Instance->Part == 0 && State->Instance->Lane == 0);
264 for (unsigned Lane = 0, VF = State->VF; Lane < VF; ++Lane) {
265 State->Instance->Lane = Lane;
H A DVPlan.h89 unsigned Lane; member in struct:llvm::VPIteration
154 assert(Instance.Lane < VF && "Queried Scalar Lane is too large.");
161 return Entry[Instance.Part][Instance.Lane] != nullptr;
175 return ScalarMapStorage[Key][Instance.Part][Instance.Lane];
201 ScalarMapStorage[Key][Instance.Part][Instance.Lane] = Scalar;
213 /// Reset the scalar value associated with \p Key for \p Part and \p Lane.
221 ScalarMapStorage[Key][Instance.Part][Instance.Lane] = Scalar;
274 /// Get the generated Value for a given VPValue and given Part and Lane. Note
H A DLoopVectorize.cpp600 /// If \p VectorLoopValue is a scalarized value, \p Lane is also specified,
615 unsigned Lane = UINT_MAX);
1779 Value *VectorLoopVal, unsigned Part, unsigned Lane) {
1799 if (Lane < UINT_MAX)
1800 VectorLoopValueMap.setScalarValue(CastInst, {Part, Lane}, VectorLoopVal);
1989 for (unsigned Lane = 0; Lane < Lanes; ++Lane) {
1990 auto *StartIdx = getSignedIntOrFpConstant(ScalarIVTy, VF * Part + Lane);
1993 VectorLoopValueMap.setScalarValue(EntryVal, {Part, Lane}, Ad
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DInterleavedAccessPass.cpp220 // Lane computes x's position in the Mask
221 unsigned Lane = J * Factor + I; local
222 unsigned NextLane = Lane + Factor;
223 int LaneValue = Mask[Lane];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1335 auto GetSwizzleSrcs = [](size_t I, const SDValue &Lane) {
1337 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1339 const SDValue &SwizzleSrc = Lane->getOperand(0);
1340 const SDValue &IndexExt = Lane->getOperand(1);
1383 const SDValue &Lane = Op->getOperand(I); local
1384 if (Lane.isUndef())
1387 AddCount(SplatValueCounts, Lane);
1389 if (IsConstant(Lane)) {
1392 auto SwizzleSrcs = GetSwizzleSrcs(I, Lane);
1420 IsLaneConstructed = [&, Swizzled](size_t I, const SDValue &Lane) {
1461 const SDValue &Lane = Op->getOperand(I); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.h433 int Lane = -1; member in struct:llvm::final::SpilledReg
436 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {}
438 bool hasLane() { return Lane != -1;}
509 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
512 : I->second.Lanes[Lane];
H A DSIFrameLowering.cpp765 .addImm(Spill[0].Lane)
866 .addImm(Spill[0].Lane);
1029 << ':' << Spill.Lane << '\n');
1047 << ':' << Spill.Lane << '\n';);
H A DSIRegisterInfo.cpp546 unsigned Lane,
554 MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane);
806 .addImm(Spill.Lane)
897 .addImm(Spill.Lane);
543 spillVGPRtoAGPR(const GCNSubtarget &ST, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill) argument
H A DSIISelLowering.cpp10136 unsigned Lane = 0; local
10171 // Lane means which subreg of %vgpra_vgprb_vgprc_vgprd is used.
10172 // Note that subregs are packed, i.e. Lane==0 is the first bit set
10173 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
10175 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
10178 if (UsesTFC && Lane == TFCLane) {
10179 Users[Lane] = *I;
10183 for (unsigned i = 0, Dmask = OldDmask; (i <= Lane) && (Dmask != 0); i++) {
10189 if (Users[Lane])
10192 Users[Lane]
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp427 // {0, Stride%(VF/Lane), (2*Stride%(VF/Lane))...(VF*Stride/Lane)%(VF/Lane),
428 // (VF/ Lane) ,(VF / Lane)+Stride%(VF/Lane),...,
429 // (VF / Lane)+(VF*Stride/Lane)%(VF/Lane)}
615 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; local
[all...]
H A DX86ISelLowering.cpp6525 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
6527 Mask.push_back(Elt + (Lane * NumEltsPerLane));
6529 Mask.push_back(Elt + (Lane * NumEltsPerLane) + Offset);
6546 for (int Lane = 0; Lane != NumLanes; ++Lane) {
6548 int OuterIdx = (Lane * NumEltsPerLane) + Elt;
6549 int InnerIdx = (Lane * NumInnerEltsPerLan
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp1694 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1695 unsigned LaneIdx = Lane * VWidthPerLane;
1699 OpDemandedElts.setBit((Lane * InnerVWidthPerLane) + Elt);
1709 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1710 APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane);
1712 LaneElts <<= InnerVWidthPerLane * (2 * Lane
[all...]
H A DInstCombineCalls.cpp604 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
606 PackMask.push_back(Elt + (Lane * NumSrcEltsPerLane));
608 PackMask.push_back(Elt + (Lane * NumSrcEltsPerLane) + NumSrcElts);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp7103 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64); local
7104 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
7226 int Lane = SVN->getSplatIndex(); local
7228 if (Lane == -1)
7229 Lane = 0;
7231 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
7237 !isa<ConstantSDNode>(V1.getOperand(Lane)))
7238 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
7275 if (getScaledOffsetDup(V1, Lane, CastVT)) {
7280 Lane
8028 SDValue Lane = Value.getOperand(1); local
10450 SDValue Lane = Op1.getOperand(1); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3177 unsigned Lane = MI.getOperand(2).getImm(); local
3179 if (Lane == 0) {
3195 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3222 unsigned Lane = MI.getOperand(2).getImm() * 2; local
3225 if (Lane == 0)
3252 unsigned Lane = MI.getOperand(2).getImm(); local
3264 .addImm(Lane)
3288 unsigned Lane = MI.getOperand(2).getImm(); local
3298 .addImm(Lane)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DConstantFolding.cpp2399 SmallVector<Constant *, 4> Lane(Operands.size());
2446 Lane[J] = Operands[J];
2454 Lane[J] = Agg;
2459 ConstantFoldScalarCall(Name, IntrinsicID, Ty, Lane, TLI, Call);
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp6836 uint32_t Lane = cast<ConstantInt>(Ops[2])->getZExtValue();
6837 Value *SV = llvm::ConstantVector::get(ConstantInt::get(Int32Ty, 1-Lane));
6846 uint32_t Indices[] = {1 - Lane, Lane};
14523 Value *Lane = llvm::ConstantInt::get(getLLVMContext(), LaneConst);
14524 Value *Extract = Builder.CreateExtractElement(Vec, Lane);
14551 Value *Lane = llvm::ConstantInt::get(getLLVMContext(), LaneConst);
14558 return Builder.CreateInsertElement(Vec, Trunc, Lane);
14564 return Builder.CreateInsertElement(Vec, Val, Lane);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp5495 int64_t Lane[LANE_NUM];
5496 if (parseSwizzleOperands(LANE_NUM, Lane, 0, LANE_MAX,
5500 Imm |= Lane[I] << (LANE_SHIFT * I);

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