Searched refs:LOAD (Results 1 - 25 of 59) sorted by relevance

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/freebsd-11-stable/contrib/ntp/sntp/libevent/
H A Devthread_win32.c114 #define LOAD(name) \ macro
116 LOAD(InitializeConditionVariable);
117 LOAD(SleepConditionVariableCS);
118 LOAD(WakeAllConditionVariable);
119 LOAD(WakeConditionVariable);
/freebsd-11-stable/usr.bin/xlint/lint1/
H A Dop.h113 LOAD, enumerator in enum:__anon13873
H A Dtree.c199 { LOAD, { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
200 "LOAD" } },
756 tn = mktnode(LOAD, tp, tn, NULL);
857 ln->tn_left->tn_op == LOAD) {
875 ln->tn_left->tn_op == LOAD) {
1129 ln->tn_left->tn_op == LOAD) {
1151 case LOAD:
3534 case LOAD:
4000 case LOAD:
/freebsd-11-stable/stand/i386/mbr/
H A Dmbr.s20 .set LOAD,0x7c00 # Load address
39 movw $LOAD,%sp # stack
44 movw $main-EXEC+LOAD,%si # Source
52 jmp main-LOAD+EXEC # To relocated code
91 movw $LOAD,%bx # Transfer buffer
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp57 LOAD = 1u << 0, member in class:__anon2125::SIMemOp
1027 if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)
1039 if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)
1152 SIMemOp::LOAD | SIMemOp::STORE,
1160 SIMemOp::LOAD,
1191 SIMemOp::LOAD | SIMemOp::STORE,
1228 SIMemOp::LOAD | SIMemOp::STORE,
1258 SIMemOp::LOAD | SIMemOp::STORE,
1269 isAtomicRet(*MI) ? SIMemOp::LOAD :
H A DAMDGPUISelLowering.cpp70 setOperationAction(ISD::LOAD, MVT::f32, Promote);
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
76 setOperationAction(ISD::LOAD, MVT::v3f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
79 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
80 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
82 setOperationAction(ISD::LOAD, MVT::v5f32, Promote);
83 AddPromotedToType(ISD::LOAD, MV
[all...]
H A DSIISelLowering.cpp176 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
177 setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
178 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
179 setOperationAction(ISD::LOAD, MVT::v5i32, Custom);
180 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
181 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
182 setOperationAction(ISD::LOAD, MVT::i1, Custom);
183 setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
259 // We only support LOAD/STORE and vector manipulation ops for vectors
266 case ISD::LOAD
[all...]
H A DR600ISelLowering.cpp72 setOperationAction(ISD::LOAD, MVT::i32, Custom);
73 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
74 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
282 setTargetDAGCombine(ISD::LOAD);
491 case ISD::LOAD: {
1497 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
2054 case ISD::LOAD: {
/freebsd-11-stable/stand/i386/pmbr/
H A Dpmbr.s37 .set LOAD,0x7c00 # Load address
76 movw $main-EXEC+LOAD,%si # Source
84 jmp main-LOAD+EXEC # To relocated code
139 movw $LOAD/16,%bx
152 jmp LOAD # Jump to boot code
/freebsd-11-stable/stand/i386/boot0/
H A Dboot0.S123 * LOAD is the original load address and cannot be changed.
134 .set LOAD,0x7c00 # Load address
175 * NOTE: the initial section of the code (up to movw $LOAD,%sp)
186 movw $LOAD,%sp # stack
208 jmp main-LOAD+ORIGIN # Jump to relocated code
483 * Load selected bootsector to the LOAD location in RAM. If read
486 3: movw $LOAD,%bx # Address for read
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp209 case ISD::LOAD:
212 unsigned int IndexResNo = (Base->getOpcode() == ISD::LOAD) ? 1 : 0;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp360 template <> bool AVRDAGToDAGISel::select<ISD::LOAD>(SDNode *N) {
545 case ISD::LOAD: return select<ISD::LOAD>(N);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp352 if (N1.getOpcode() == ISD::LOAD &&
404 case ISD::LOAD:
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h668 /// LOAD and STORE have token chains as their first operand, then the same
672 LOAD, STORE, enumerator in enum:llvm::ISD::NodeType
H A DSelectionDAGNodes.h1395 return N->getOpcode() == ISD::LOAD ||
2201 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
2217 return N->getOpcode() == ISD::LOAD ||
2222 /// This class is used to represent ISD::LOAD nodes.
2229 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2246 return N->getOpcode() == ISD::LOAD;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.cpp296 case ISD::LOAD:
/freebsd-11-stable/sys/contrib/zlib/
H A Dinfback.c128 #define LOAD() \ macro
488 LOAD();
H A Dinflate.c476 #define LOAD() \ macro
651 LOAD();
1048 LOAD();
/freebsd-11-stable/contrib/binutils/ld/
H A Dldlex.l331 <MRI>"LOAD" { RTOKEN(LOAD); }
348 <MRI>"load" { RTOKEN(LOAD); }
H A Dldgram.y147 %token CHIP LIST SECT ABSOLUTE LOAD NEWLINE ENDWORD ORDER NAMEWORD ASSERT_K
236 | LOAD mri_load_name_list
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp885 case ISD::LOAD: return SelectLoad(N);
965 if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) {
1094 if (Opc != ISD::LOAD && Opc != ISD::STORE)
1096 SDValue Addr = Opc == ISD::LOAD ? N->getOperand(1) : N->getOperand(2);
1467 case ISD::LOAD: {
2246 if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE)
2291 if (N->getOpcode() == ISD::LOAD)
H A DHexagonISelLoweringHVX.cpp90 setOperationAction(ISD::LOAD, T, Custom);
142 setOperationAction(ISD::LOAD, T, Custom);
1506 if (MemOpc == ISD::LOAD) {
1536 case ISD::LOAD:
1584 case ISD::LOAD: return SDValue();
/freebsd-11-stable/sys/cddl/contrib/opensolaris/uts/common/zmod/
H A Dinflate.c410 #define LOAD() \ macro
590 LOAD();
975 LOAD();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp333 if (Opcode == ISD::LOAD)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp85 case ISD::LOAD:
1296 case ISD::LOAD:
1372 case ISD::LOAD:
1442 case ISD::LOAD:
1518 case ISD::LOAD:
1588 case ISD::LOAD:

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