Searched refs:LH (Results 1 - 18 of 18) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaStmtAttr.cpp193 const LoopHintAttr *LH = dyn_cast<LoopHintAttr>(I); local
196 if (!LH)
199 LoopHintAttr::OptionType Option = LH->getOption();
250 CategoryState.StateAttr = LH;
254 CategoryState.NumericAttr = LH;
258 SourceLocation OptionLoc = LH->getRange().getBegin();
263 << LH->getDiagnosticName(Policy);
H A DSemaTemplateInstantiate.cpp1055 const LoopHintAttr *TransformLoopHintAttr(const LoopHintAttr *LH);
1451 TemplateInstantiator::TransformLoopHintAttr(const LoopHintAttr *LH) { argument
1452 Expr *TransformedExpr = getDerived().TransformExpr(LH->getValue()).get();
1454 if (TransformedExpr == LH->getValue())
1455 return LH;
1458 if (getSema().CheckLoopHintExpr(TransformedExpr, LH->getLocation()))
1459 return LH;
1463 return LoopHintAttr::CreateImplicit(getSema().Context, LH->getOption(),
1464 LH->getState(), TransformedExpr, *LH);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp506 SDValue LL, LH, RL, RH, CL, CH; local
508 GetSplitOp(N->getOperand(1), LL, LH);
539 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH);
544 SDValue LL, LH, RL, RH; local
546 GetSplitOp(N->getOperand(2), LL, LH);
551 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
552 N->getOperand(1), LH, RH, N->getOperand(4));
H A DTargetLowering.cpp5742 SDValue LH, SDValue RL, SDValue RH) const {
5763 // LL, LH, RL, and RH must be either all NULL or all set to a value.
5764 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
5765 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
5831 if (!LH.getNode() && !RH.getNode() &&
5834 LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift);
5835 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
5840 if (!LH.getNode())
5850 LH
[all...]
H A DLegalizeIntegerTypes.cpp2922 SDValue LL, LH, RL, RH; local
2923 GetExpandedInteger(N->getOperand(0), LL, LH);
2926 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2935 SDValue LL, LH, RL, RH; local
2936 GetExpandedInteger(N->getOperand(0), LL, LH);
2941 LL, LH, RL, RH))
2999 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
3082 SDValue LL, LH, RL, RH; local
3083 GetExpandedInteger(LHS, LL, LH);
3090 LL, LH, R
[all...]
H A DLegalizeVectorTypes.cpp1677 SDValue LL, LH, RL, RH; local
1680 GetSplitVector(N->getOperand(0), LL, LH);
1682 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1691 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGLoopInfo.cpp581 const LoopHintAttr *LH = dyn_cast<LoopHintAttr>(Attr); local
586 if (!LH && !OpenCLHint) {
607 } else if (LH) {
608 auto *ValueExpr = LH->getValue();
614 Option = LH->getOption();
615 State = LH->getState();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp222 case Mips::LH:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp220 case RISCV::LH:
H A DRISCVMergeBaseOffset.cpp213 case RISCV::LH:
H A DRISCVInstrInfo.cpp46 case RISCV::LH:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp676 SDValue LH, RH; local
677 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
686 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
688 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp207 return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu;
H A DMipsSEISelLowering.cpp3584 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4053 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4060 SDValue LL = SDValue(), SDValue LH = SDValue(),
4068 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4074 SDValue LL = SDValue(), SDValue LH = SDValue(),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1840 emitLoadStoreSymbol(Inst, RISCV::LH, IDLoc, Out, /*HasTmpReg=*/false);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp196 // are low registers, otherwise use RISB[LH]G.
242 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
1248 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
H A DSystemZISelLowering.cpp3469 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63); local
3477 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);

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