/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { argument 74 switch ((Imm >> 6) & 0x7) { 85 static inline unsigned getShiftValue(unsigned Imm) { argument 86 return Imm & 0x3f; 99 unsigned Imm) { 100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); 110 return (STEnc << 6) | (Imm & 0x3f); 118 static inline unsigned getArithShiftValue(unsigned Imm) { argument 119 return Imm 98 getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm) argument 123 getExtendType(unsigned Imm) argument 138 getArithExtendType(unsigned Imm) argument 170 getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm) argument 178 getMemDoShift(unsigned Imm) argument 184 getMemExtendType(unsigned Imm) argument 213 processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding) argument 343 getFPImmFloat(unsigned Imm) argument 367 getFP16Imm(const APInt &Imm) argument 393 getFP32Imm(const APInt &Imm) argument 421 getFP64Imm(const APInt &Imm) argument 451 isAdvSIMDModImmType1(uint64_t Imm) argument 456 encodeAdvSIMDModImmType1(uint64_t Imm) argument 460 decodeAdvSIMDModImmType1(uint8_t Imm) argument 466 isAdvSIMDModImmType2(uint64_t Imm) argument 471 encodeAdvSIMDModImmType2(uint64_t Imm) argument 475 decodeAdvSIMDModImmType2(uint8_t Imm) argument 481 isAdvSIMDModImmType3(uint64_t Imm) argument 486 encodeAdvSIMDModImmType3(uint64_t Imm) argument 490 decodeAdvSIMDModImmType3(uint8_t Imm) argument 496 isAdvSIMDModImmType4(uint64_t Imm) argument 501 encodeAdvSIMDModImmType4(uint64_t Imm) argument 505 decodeAdvSIMDModImmType4(uint8_t Imm) argument 511 isAdvSIMDModImmType5(uint64_t Imm) argument 517 encodeAdvSIMDModImmType5(uint64_t Imm) argument 521 decodeAdvSIMDModImmType5(uint8_t Imm) argument 527 isAdvSIMDModImmType6(uint64_t Imm) argument 533 encodeAdvSIMDModImmType6(uint64_t Imm) argument 537 decodeAdvSIMDModImmType6(uint8_t Imm) argument 543 isAdvSIMDModImmType7(uint64_t Imm) argument 548 encodeAdvSIMDModImmType7(uint64_t Imm) argument 552 decodeAdvSIMDModImmType7(uint8_t Imm) argument 558 isAdvSIMDModImmType8(uint64_t Imm) argument 563 decodeAdvSIMDModImmType8(uint8_t Imm) argument 568 encodeAdvSIMDModImmType8(uint64_t Imm) argument 573 isAdvSIMDModImmType9(uint64_t Imm) argument 579 encodeAdvSIMDModImmType9(uint64_t Imm) argument 583 decodeAdvSIMDModImmType9(uint8_t Imm) argument 593 isAdvSIMDModImmType10(uint64_t Imm) argument 613 encodeAdvSIMDModImmType10(uint64_t Imm) argument 641 decodeAdvSIMDModImmType10(uint8_t Imm) argument 655 isAdvSIMDModImmType11(uint64_t Imm) argument 662 encodeAdvSIMDModImmType11(uint64_t Imm) argument 690 decodeAdvSIMDModImmType11(uint8_t Imm) argument 705 isAdvSIMDModImmType12(uint64_t Imm) argument 711 encodeAdvSIMDModImmType12(uint64_t Imm) argument 739 decodeAdvSIMDModImmType12(uint8_t Imm) argument 755 isSVEMaskOfIdenticalElements(int64_t Imm) argument 762 isSVECpyImm(int64_t Imm) argument 777 isSVEAddSubImm(int64_t Imm) argument 784 isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Utils/ |
H A D | RISCVMatInt.h | 22 int64_t Imm; member in struct:llvm::RISCVMatInt::Inst 24 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} argument
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVTargetTransformInfo.cpp | 18 int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { argument 23 if (Imm == 0) 28 return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), 32 int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, argument 38 if (Imm == 0) 74 if (Imm.getMinSignedBits() <= 64 && 75 getTLI()->isLegalAddImmediate(Imm.getSExtValue())) { 81 return getIntImmCost(Imm, Ty); 89 const APInt &Imm, Type *Ty) { 88 getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) argument
|
H A D | RISCVTargetTransformInfo.h | 44 int getIntImmCost(const APInt &Imm, Type *Ty); 45 int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty); 46 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.cpp | 32 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument 34 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); 35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 38 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument 40 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); 41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); 44 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument 46 unsigned Shamt = countTrailingZeros(Imm); 47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); 51 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument 129 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument [all...] |
H A D | MipsAnalyzeImmediate.h | 26 /// Analyze - Get an instruction sequence to load immediate Imm. The last 29 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); 38 /// load immediate Imm 39 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 42 /// load immediate Imm 43 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 46 /// load immediate Imm 47 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 49 /// GetInstSeqLs - Get instruction sequences to load immediate Imm. 50 void GetInstSeqLs(uint64_t Imm, unsigne [all...] |
H A D | MipsISelDAGToDAG.h | 98 virtual bool selectVSplat(SDNode *N, APInt &Imm, 101 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const; 103 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const; 105 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const; 107 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const; 109 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const; 111 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const; 113 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const; 115 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const; 117 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons 138 getImm(const SDNode *Node, uint64_t Imm) argument [all...] |
H A D | MipsSEISelDAGToDAG.h | 96 bool selectVSplat(SDNode *N, APInt &Imm, 99 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, 102 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override; 104 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override; 106 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override; 108 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override; 110 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override; 112 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override; 114 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override; 116 bool selectVSplatSimm5(SDValue N, SDValue &Imm) cons [all...] |
H A D | MipsISelDAGToDAG.cpp | 154 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, argument 160 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { 165 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { 170 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { 175 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { 180 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { 185 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { 190 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { 195 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { 200 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 113 return ShOp | (Imm << 3); 120 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } 123 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } 125 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 129 inline unsigned getSOImmValRotate(unsigned Imm) { argument 132 if ((Imm & ~255U) == 0) return 0; 135 unsigned TZ = countTrailingZeros(Imm); 210 getThumbImmValShift(unsigned Imm) argument 229 getThumbImm16ValShift(unsigned Imm) argument 263 unsigned u, Vs, Imm; local 327 isT2SOImmTwoPartVal(unsigned Imm) argument 354 getT2SOImmTwoPartFirst(unsigned Imm) argument 371 getT2SOImmTwoPartSecond(unsigned Imm) argument 630 getFPImmFloat(unsigned Imm) argument 653 getFP16Imm(const APInt &Imm) argument 679 getFP32Imm(const APInt &Imm) argument 707 getFP64Imm(const APInt &Imm) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.h | 30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 51 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, 54 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, 57 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, 60 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm, 66 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, 72 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, 78 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, 87 void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, 115 void DecodeBLENDMask(unsigned NumElts, unsigned Imm, [all...] |
H A D | X86ShuffleDecode.cpp | 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 31 unsigned ZMask = Imm & 15; 32 unsigned CountD = (Imm >> 4) & 3; 33 unsigned CountS = (Imm >> 6) & 3; 96 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, argument 103 if (i >= Imm) M = i - Imm + l; 108 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, argument 114 unsigned Base = i + Imm; 121 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, argument 135 DecodeVALIGNMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 147 DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 163 DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 177 DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 203 DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 277 decodeVSHUF64x2FamilyMask(unsigned NumElts, unsigned ScalarSize, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 294 DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 328 DecodeBLENDMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 378 DecodeVPERMMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandImm.h | 28 void expandMOVImm(uint64_t Imm, unsigned BitSize,
|
H A D | AArch64ExpandImm.cpp | 23 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { argument 26 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; 126 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { argument 131 Imm &= ~(Mask << (Idx * 16)); 134 Imm |= Mask << (Idx * 16); 136 return Imm; 246 static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize, argument 260 Imm = ~Imm; 265 Imm 305 expandMOVImm(uint64_t Imm, unsigned BitSize, SmallVectorImpl<ImmInsnModel> &Insn) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiTargetTransformInfo.h | 52 int getIntImmCost(const APInt &Imm, Type *Ty) { argument 54 if (Imm == 0) 56 if (isInt<16>(Imm.getSExtValue())) 58 if (isInt<21>(Imm.getZExtValue())) 60 if (isInt<32>(Imm.getSExtValue())) { 61 if ((Imm.getSExtValue() & 0xFFFF) == 0) 69 int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) { argument 70 return getIntImmCost(Imm, Ty); 73 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, argument 75 return getIntImmCost(Imm, T [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/ |
H A D | NVPTXInstPrinter.cpp | 101 int64_t Imm = MO.getImm(); local 105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) 109 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) 113 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { 151 int64_t Imm = MO.getImm(); local 155 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) 158 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { 225 int Imm = (int) MO.getImm(); local 227 if (Imm) 230 switch (Imm) { 276 int Imm = (int)MO.getImm(); local 278 O << Imm; // Just print out PTX version local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 32 int64_t Imm = Inst.getOperand(0).getImm(); 33 Target = Addr+Size+Imm;
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 171 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { 172 if (!isUInt<N>(Imm)) 174 Inst.addOperand(MCOperand::createImm(Imm)); 179 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { 180 if (!isUInt<N>(Imm)) 182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 186 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, 188 return decodeUImmOperand<1>(Inst, Imm); 191 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, 193 return decodeUImmOperand<2>(Inst, Imm); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.cpp | 53 int64_t Imm = MI->getOperand(OpNo).getImm(); local 54 if (isInt<16>(Imm) || isUInt<16>(Imm)) 55 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); 114 uint16_t Imm = MI->getOperand(OpNo).getImm(); local 115 if (Imm != 0) { 124 uint16_t Imm = MI->getOperand(OpNo).getImm(); local 125 if (Imm != 0) { 349 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm, argument 352 int16_t SImm = static_cast<int16_t>(Imm); 381 printImmediateV216(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument 388 printImmediate32(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument 422 printImmediate64(uint64_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument 464 unsigned Imm = MI->getOperand(OpNo).getImm(); local 474 unsigned Imm = MI->getOperand(OpNo).getImm(); local 484 unsigned Imm = MI->getOperand(OpNo).getImm(); local 688 unsigned Imm = MI->getOperand(OpNo).getImm(); local 701 unsigned Imm = MI->getOperand(OpNo).getImm(); local 798 unsigned Imm = MI->getOperand(OpNo).getImm(); local 808 unsigned Imm = MI->getOperand(OpNo).getImm(); local 818 unsigned Imm = MI->getOperand(OpNo).getImm(); local 858 unsigned Imm = MI->getOperand(OpNo).getImm(); local 1037 unsigned Imm = MI->getOperand(OpNum).getImm(); local 1049 O << "invalid_param_" << Imm; local 1135 int Imm = MI->getOperand(OpNo).getImm(); local 1336 uint16_t Imm = MI->getOperand(OpNo).getImm(); local 1425 int64_t Imm = Op.getImm(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFInstPrinter.cpp | 76 auto Imm = OffsetOp.getImm(); local 77 if (Imm >= 0) 78 O << " + " << formatImm(Imm); 80 O << " - " << formatImm(-Imm); 101 int16_t Imm = Op.getImm(); local 102 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 63 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, argument 66 int32_t Offset = SignExtend32<24>(Imm); 179 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 181 assert(isUInt<N>(Imm) && "Invalid immediate"); 182 Inst.addOperand(MCOperand::createImm(Imm)); 187 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 189 assert(isUInt<N>(Imm) && "Invalid immediate"); 190 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 194 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 199 uint64_t Base = Imm >> 1 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 246 ImmOp Imm; member in union:__anon2376::RISCVOperand::__anon2377 263 Imm = o.Imm; 285 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, argument 289 return RE->evaluateAsConstant(Imm); 294 Imm = CE->getValue(); 304 int64_t Imm; local 308 bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); 311 IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); 313 IsValid = isShiftedInt<N - 1, 1>(Imm); 320 int64_t Imm; local 330 int64_t Imm; local 341 int64_t Imm; local 392 int64_t Imm; local 406 int64_t Imm; local 417 int64_t Imm; local 430 int64_t Imm; local 439 int64_t Imm; local 452 int64_t Imm; local 462 int64_t Imm; local 533 int64_t Imm; local 564 int64_t Imm; local 582 int64_t Imm; local 701 int64_t Imm = 0; local 727 unsigned Imm = 0; local 1095 int64_t Imm = CE->getValue(); local 1812 int64_t Imm = Inst.getOperand(1).getImm(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 170 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, argument 172 assert(isUInt<N>(Imm) && "Invalid immediate"); 174 Inst.addOperand(MCOperand::createImm(Imm)); 179 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, argument 182 if (Imm == 0) 184 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder); 188 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, argument 190 assert(isUInt<N>(Imm) && "Invalid immediate"); 192 // Sign-extend the number in the bottom N bits of Imm 193 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 198 decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 207 decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 218 decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 229 decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MIRFormatter.h | 38 Optional<unsigned> OpIdx, int64_t Imm) const { 39 OS << Imm; local 45 StringRef Src, int64_t &Imm, 44 parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, StringRef Src, int64_t &Imm, ErrorCallbackType ErrorCallback) const argument
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegNumbering.cpp | 78 int64_t Imm = MI.getOperand(1).getImm(); local 80 << " -> WAReg " << Imm << "\n"); 81 MFI.setWAReg(MI.getOperand(0).getReg(), Imm);
|