Searched refs:IR (Results 1 - 25 of 57) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp43 bool ExecuteStage::isAvailable(const InstRef &IR) const {
44 if (Scheduler::Status S = HWS.isAvailable(IR)) {
46 notifyEvent<HWStallEvent>(HWStallEvent(ET, IR));
53 Error ExecuteStage::issueInstruction(InstRef &IR) { argument
58 HWS.issueInstruction(IR, Used, Pending, Ready);
59 Instruction &IS = *IR.getInstruction();
62 notifyReservedOrReleasedBuffers(IR, /* Reserved */ false);
64 notifyInstructionIssued(IR, Used);
66 notifyInstructionExecuted(IR);
68 if (Error S = moveToTheNextStage(IR))
81 InstRef IR = HWS.select(); local
161 verifyInstructionEliminated(const InstRef &IR) argument
173 handleInstructionEliminated(InstRef &IR) argument
186 execute(InstRef &IR) argument
252 notifyInstructionIssued( const InstRef &IR, MutableArrayRef<std::pair<ResourceRef, ResourceCycles>> Used) const argument
272 notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const argument
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H A DDispatchStage.cpp38 void DispatchStage::notifyInstructionDispatched(const InstRef &IR, argument
41 LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: #" << IR << '\n');
43 HWInstructionDispatchedEvent(IR, UsedRegs, UOps));
46 bool DispatchStage::checkPRF(const InstRef &IR) const {
48 for (const WriteState &RegDef : IR.getInstruction()->getDefs())
55 HWStallEvent(HWStallEvent::RegisterFileStall, IR));
62 bool DispatchStage::checkRCU(const InstRef &IR) const {
63 const unsigned NumMicroOps = IR.getInstruction()->getNumMicroOps();
67 HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
71 bool DispatchStage::canDispatch(const InstRef &IR) cons
78 dispatch(InstRef IR) argument
175 execute(InstRef &IR) argument
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H A DMicroOpQueueStage.cpp22 InstRef IR = Buffer[CurrentInstructionSlotIdx]; local
23 while (IR && checkNextStage(IR)) {
24 if (llvm::Error Val = moveToTheNextStage(IR))
28 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);
32 IR = Buffer[CurrentInstructionSlotIdx];
46 Error MicroOpQueueStage::execute(InstRef &IR) { argument
47 Buffer[NextAvailableSlotIdx] = IR;
48 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);
H A DRetireStage.cpp37 notifyInstructionRetired(Current.IR);
45 llvm::Error RetireStage::execute(InstRef &IR) { argument
46 RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
50 void RetireStage::notifyInstructionRetired(const InstRef &IR) const {
51 LLVM_DEBUG(llvm::dbgs() << "[E] Instruction Retired: #" << IR << '\n');
53 const Instruction &Inst = *IR.getInstruction();
57 LSU.onInstructionRetired(IR);
61 notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs));
H A DInstructionTables.cpp22 Error InstructionTables::execute(InstRef &IR) { argument
23 const InstrDesc &Desc = IR.getInstruction()->getDesc();
63 HWInstructionIssuedEvent Event(IR, UsedResources);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) { argument
42 Resources->canBeDispatched(IR.getInstruction()->getUsedBuffers());
55 LSUnit::Status LSS = LSU.isAvailable(IR);
71 InstRef &IR,
73 Instruction *IS = IR.getInstruction();
82 IS->execute(IR.getSourceIndex());
87 LSU.onInstructionIssued(IR);
93 IssuedSet.emplace_back(IR);
95 LSU.onInstructionExecuted(IR);
100 InstRef &IR,
70 issueInstructionImpl( InstRef &IR, SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources) argument
99 issueInstruction( InstRef &IR, SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources, SmallVectorImpl<InstRef> &PendingInstructions, SmallVectorImpl<InstRef> &ReadyInstructions) argument
124 InstRef &IR = *I; local
160 InstRef &IR = *I; local
195 InstRef &IR = ReadySet[I]; local
221 InstRef &IR = *I; local
300 dispatch(InstRef &IR) argument
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H A DRetireControlUnit.cpp41 unsigned RetireControlUnit::dispatch(const InstRef &IR) { argument
42 const Instruction &Inst = *IR.getInstruction();
47 Queue[NextAvailableSlotIdx] = {IR, Entries, false};
58 const Instruction *Inst = Current.IR.getInstruction();
76 Current.IR.getInstruction()->retire();
87 assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");
H A DLSUnit.cpp69 unsigned LSUnit::dispatch(const InstRef &IR) { argument
70 const InstrDesc &Desc = IR.getInstruction()->getDesc();
153 LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const {
154 const InstrDesc &Desc = IR.getInstruction()->getDesc();
162 void LSUnitBase::onInstructionExecuted(const InstRef &IR) { argument
163 unsigned GroupID = IR.getInstruction()->getLSUTokenID();
171 void LSUnitBase::onInstructionRetired(const InstRef &IR) { argument
172 const InstrDesc &Desc = IR.getInstruction()->getDesc();
179 LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << IR.getSourceIndex()
185 LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << IR
190 onInstructionExecuted(const InstRef &IR) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DDispatchStage.h59 bool checkRCU(const InstRef &IR) const;
60 bool checkPRF(const InstRef &IR) const;
61 bool canDispatch(const InstRef &IR) const;
62 Error dispatch(InstRef IR);
64 void notifyInstructionDispatched(const InstRef &IR,
73 bool isAvailable(const InstRef &IR) const override;
79 Error execute(InstRef &IR) override;
H A DExecuteStage.h37 Error issueInstruction(InstRef &IR);
44 Error handleInstructionEliminated(InstRef &IR);
62 bool isAvailable(const InstRef &IR) const override;
73 Error execute(InstRef &IR) override;
76 const InstRef &IR,
78 void notifyInstructionExecuted(const InstRef &IR) const;
79 void notifyInstructionPending(const InstRef &IR) const;
80 void notifyInstructionReady(const InstRef &IR) const;
84 void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
H A DMicroOpQueueStage.h54 unsigned getNormalizedOpcodes(const InstRef &IR) const {
57 IR.getInstruction()->getDesc().NumMicroOps);
67 bool isAvailable(const InstRef &IR) const override {
70 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);
80 Error execute(InstRef &IR) override;
H A DStage.h41 /// Returns true if it can execute IR during this cycle.
42 virtual bool isAvailable(const InstRef &IR) const { return true; }
54 /// The primary action that this stage performs on instruction IR.
55 virtual Error execute(InstRef &IR) = 0;
62 bool checkNextStage(const InstRef &IR) const {
63 return NextInSequence && NextInSequence->isAvailable(IR);
70 Error moveToTheNextStage(InstRef &IR) { argument
71 assert(checkNextStage(IR) && "Next stage is not ready!");
72 return NextInSequence->execute(IR);
H A DEntryStage.h41 bool isAvailable(const InstRef &IR) const override;
43 Error execute(InstRef &IR) override;
H A DRetireStage.h42 Error execute(InstRef &IR) override;
43 void notifyInstructionRetired(const InstRef &IR) const;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Passes/
H A DStandardInstrumentations.cpp10 /// This file defines IR-printing pass instrumentation callbacks as well as
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/IRPrintingPasses.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/IR/PassInstrumentation.h"
32 /// Extracting Module out of \p IR unit. Also fills a textual description
33 /// of \p IR for use in header when printing.
34 Optional<std::pair<const Module *, std::string>> unwrapModule(Any IR) { argument
35 if (any_isa<const Module *>(IR))
36 return std::make_pair(any_cast<const Module *>(IR), st
106 unwrapAndPrint(Any IR, StringRef Banner, bool ForceModule = false) argument
150 pushModuleDesc(StringRef PassID, Any IR) argument
167 printBeforePass(StringRef PassID, Any IR) argument
186 printAfterPass(StringRef PassID, Any IR) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h103 void onGroupIssued(const InstRef &IR) { argument
107 unsigned Cycles = IR.getInstruction()->getCyclesLeft();
109 CriticalPredecessor.IID = IR.getSourceIndex();
120 void onInstructionIssued(const InstRef &IR) { argument
125 const Instruction &IS = *IR.getInstruction();
129 CriticalMemoryInstruction = IR;
131 CriticalMemoryInstruction = IR;
228 /// accomodate instruction IR. By default, LSU_AVAILABLE is returned if IR is
230 virtual Status isAvailable(const InstRef &IR) cons
302 onInstructionIssued(const InstRef &IR) argument
[all...]
H A DScheduler.h138 InstRef &IR,
181 /// Check if the instruction in 'IR' can be dispatched during this cycle.
185 /// IR cannot be dispatched to the Scheduler due to unavailable resources.
186 Status isAvailable(const InstRef &IR);
191 /// Returns true if instruction IR is ready to be issued to the underlying
193 /// previous call to method `isAvailable(IR)` returned `SC_AVAILABLE`.
195 /// If IR is a memory operation, then the Scheduler queries the LS unit to
198 bool dispatch(InstRef &IR);
204 InstRef &IR,
209 /// Returns true if IR ha
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/
H A DHWEventListener.h53 : Type(type), IR(Inst) {}
59 const InstRef &IR; member in class:llvm::mca::HWInstructionEvent
65 HWInstructionIssuedEvent(const InstRef &IR, argument
67 : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {}
74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, argument
76 : HWInstructionEvent(HWInstructionEvent::Dispatched, IR),
83 // the instruction descriptor of IR.
84 // The only exception is when IR declares a number of micro opcodes
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) argument
96 : HWInstructionEvent(HWInstructionEvent::Retired, IR),
126 const InstRef &IR; member in class:llvm::mca::HWStallEvent
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Passes/
H A DStandardInstrumentations.h19 #include "llvm/IR/PassInstrumentation.h"
20 #include "llvm/IR/PassTimingInfo.h"
29 /// Instrumentation to print IR before/after passes.
31 /// Needs state to be able to print module after pass that invalidates IR unit
41 bool printBeforePass(StringRef PassID, Any IR);
42 void printAfterPass(StringRef PassID, Any IR);
47 void pushModuleDesc(StringRef PassID, Any IR);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DPassManager.h12 /// which supports a method to 'run' it over a unit of IR can be used as
14 /// which run over a particular IR construct, and run each of them in sequence
15 /// over each such construct in the containing IR construct. As there is no
16 /// containing IR construct for a Module, a manager for passes over modules
20 /// The core IR library provides managers for running passes over
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/IR/PassInstrumentation.h"
47 #include "llvm/IR/PassManagerInternal.h"
84 /// particular IR uni
420 getAnalysisResultUnpackTuple(AnalysisManagerT &AM, IRUnitT &IR, std::tuple<ArgTs...> Args, std::index_sequence<Ns...>) argument
435 getAnalysisResult(AnalysisManager<IRUnitT, AnalysisArgTs...> &AM, IRUnitT &IR, std::tuple<MainArgTs...> Args) argument
489 run(IRUnitT &IR, AnalysisManagerT &AM, ExtraArgTs... ExtraArgs) argument
667 invalidate(IRUnitT &IR, const PreservedAnalyses &PA) argument
681 invalidate(AnalysisKey *ID, IRUnitT &IR, const PreservedAnalyses &PA) argument
689 invalidateImpl(AnalysisKey *ID, IRUnitT &IR, const PreservedAnalyses &PA) argument
747 clear(IRUnitT &IR, llvm::StringRef Name) argument
777 getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs) argument
849 invalidate(IRUnitT &IR) argument
852 invalidateImpl(PassT::ID(), IR); local
859 invalidate(IRUnitT &IR, const PreservedAnalyses &PA) argument
939 getResultImpl(AnalysisKey *ID, IRUnitT &IR, ExtraArgTs... ExtraArgs) argument
984 invalidateImpl(AnalysisKey *ID, IRUnitT &IR) argument
1108 run(IRUnitT &IR, AnalysisManager<IRUnitT, ExtraArgTs...> &AM, ExtraArgTs...) argument
1416 run(IRUnitT &IR, AnalysisManagerT &AM, Ts &&... Args) argument
[all...]
H A DPassInstrumentation.h1 //===- llvm/IR/PassInstrumentation.h ----------------------*- C++ -*-===//
40 /// 'const IRUnitT*' so as to avoid any accidental changes to IR in
141 /// and constant reference to IR it operates on. \Returns true if pass is
144 bool runBeforePass(const PassT &Pass, const IRUnitT &IR) const {
150 ShouldRun &= C(Pass.name(), llvm::Any(&IR));
155 /// just been executed and constant reference to \p IR it operates on.
156 /// \p IR is guaranteed to be valid at this point.
158 void runAfterPass(const PassT &Pass, const IRUnitT &IR) const {
161 C(Pass.name(), llvm::Any(&IR));
165 /// that has just been executed. For use when IR ha
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/freebsd-11-stable/share/i18n/csmapper/GB/
H A DMakefile7 GBKEXT%UCS.mps GBKUDA%UCS.mps ISO-IR-165EXT%UCS.mps \
10 UCS%ISO-IR-165EXT.mps
/freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DSchedulerStatistics.h82 void onReservedBuffers(const InstRef &IR,
87 void onReleasedBuffers(const InstRef &IR,
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Transforms/IPO/
H A DThinLTOBitcodeWriter.h19 #include <llvm/IR/PassManager.h>
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/
H A DPipeline.cpp60 InstRef IR; local
62 while (!Err && FirstStage.isAvailable(IR))
63 Err = FirstStage.execute(IR);

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